Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10461075 | Embedded tungsten resistor | Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith E. Kunz | 2019-10-29 |
| 9985018 | Embedded tungsten resistor | Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith E. Kunz | 2018-05-29 |
| 9966373 | MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts | Kamel Benaissa | 2018-05-08 |
| 9741724 | SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array | Anand Seshadri, Steve Prins | 2017-08-22 |
| 9589983 | Efficient buried oxide layer interconnect scheme | — | 2017-03-07 |
| 9583609 | MOS transistor structure and method of forming the structure with vertically and horizontally-elongated metal contacts | Kamel Benaissa | 2017-02-28 |
| 9385140 | Efficient buried oxide layer interconnect scheme | — | 2016-07-05 |
| 9209195 | SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array | Anand Seshadri, Steve Prins | 2015-12-08 |
| 9184226 | Embedded tungsten resistor | Binu Kamblath Pushkarakshan, Subramanian J. Narayan, Swaminathan Sankaran, Keith E. Kunz | 2015-11-10 |
| 9093315 | CMOS process to improve SRAM yield | Shaofeng Yu, Wah Kit Loh | 2015-07-28 |
| 8962419 | Complementary stress memorization technique layer method | Dong-Joo Bae | 2015-02-24 |
| 8871587 | Complementary stress memorization technique layer method | Dong-Joo Bae | 2014-10-28 |
| 8603875 | CMOS process to improve SRAM yield | Shaofeng Yu, Wah Kit Loh | 2013-12-10 |
| 8379435 | Smart well assisted SRAM read and write | Theodore W. Houston | 2013-02-19 |