Issued Patents All Time
Showing 51–75 of 228 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10270487 | Frequency generator and associated method | Chia-Chun Liao, Min-Shueh Yuan, Chao Li | 2019-04-23 |
| 10270486 | Ultra-low power receiver | Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Lan-Chou Cho, Sandro Binsfeld Ferreira | 2019-04-23 |
| 10171089 | PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications | Feng-Wei Kuo, Chewn-Pu Jou, Lan-Chou Cho, Huan-Neng Chen, Seyednaser Pourmousavian | 2019-01-01 |
| 10122371 | Reconfigurable calculation unit with atomic computation units and control inputs | Roman Staszewski, Fuqiang Shi | 2018-11-06 |
| 10110195 | CMOS tuner and related tuning algorithm for a passive adaptive antenna matching network suitable for use with agile RF transceivers | Armin Tavakol | 2018-10-23 |
| 10101709 | Time register | Ying-Cheng Wu, Yihong Mao | 2018-10-16 |
| 10079608 | Time-to-digital converter and method therefor | Priyanka Kumar, Edoardo Charbon | 2018-09-18 |
| 10056881 | Charge sharing filter | Iman Madadi, Massoud Tohidian | 2018-08-21 |
| 10008980 | Wideband digitally controlled injection-locked oscillator | Imran Bashir | 2018-06-26 |
| 9989928 | Time-to-digital converter | Ying-Cheng Wu, Yihong Mao | 2018-06-05 |
| 9929885 | Phase tracking receiver | Vijay Kumar Purushothaman, Yao-Hong Liu | 2018-03-27 |
| 9893735 | Digital phase locked loop | Dirk Leipold | 2018-02-13 |
| 9853649 | Phase domain calculator clock, ALU, memory, register file, sequencer, latches | Roman Staszewski, Fuqiang Shi | 2017-12-26 |
| 9831847 | Transformer based impedance matching network and related power amplifier, ADPLL and transmitter based thereon | Masoud Babaie | 2017-11-28 |
| 9722537 | Fractional-N frequency synthesizer incorporating cyclic digital-to-time and time-to-digital circuit pair | Gerasimos S. Vlachogiannakis, Augusto Ronchini Ximenes | 2017-08-01 |
| 9685910 | Transformer based impedance matching network and related power amplifier, ADPLL and transmitter based thereon | Masoud Babaie | 2017-06-20 |
| 9680486 | DCO phase noise with PVT-insensitive calibration circuit in ADPLL applications | Feng-Wei Kuo, Kuang-Kai Yen, Jinn-Yeh Chien, Chewn-Pu Jou | 2017-06-13 |
| 9680487 | RF circuit, DCO, frequency divider with three divided clock outputs | Dirk Leipold | 2017-06-13 |
| 9641164 | Quadrature LC tank digitally controlled ring oscillator | Massoud Tohidian, Ali Fotowat Ahmady, Seyed Amir Reza Ahmadi Mehr, Mahmoud Kamarei, Fabien Ndagijimana | 2017-05-02 |
| 9634610 | 60 GHz wideband class E/F2 power amplifier | Masoud Babaie | 2017-04-25 |
| 9590646 | Frequency synthesizers with adjustable delays | Yuan Gao, Frank Leong | 2017-03-07 |
| 9584141 | All digital phase-locked loop | Feng-Wei Kuo, Chewn-Pu Jou, Huan-Neng Chen, Kuang-Kai Yen, Lan-Chou Cho +1 more | 2017-02-28 |
| 9473155 | Software reconfigurable digital phase lock loop architecture | Roman Staszewski, Fuqiang Shi | 2016-10-18 |
| 9455667 | Fractional-N all digital phase locked loop incorporating look ahead time to digital converter | Gerasimos S. Vlachogiannakis, Augusto Ronchini Ximenes | 2016-09-27 |
| 9444433 | Wideband FM demodulation by injection-locked division of frequency deviation | Akshay Visweswaran, John R. Long | 2016-09-13 |