Issued Patents All Time
Showing 26–50 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9596109 | Methods and systems for high bandwidth communications interface | John Fox, Brian Holden, Ali Hormati, Peter Hunt, John D. Keay +5 more | 2017-03-14 |
| 9577815 | Clock data alignment system for vector signaling code communications link | Andrew Kevin John Stewart, Ali Hormati | 2017-02-21 |
| 9450744 | Control loop management and vector signaling code communications links | Roger Ulrich | 2016-09-20 |
| 9363114 | Clock-embedded vector signaling codes | Amin Shokrollahi, Brian Holden | 2016-06-07 |
| 9362962 | Methods and systems for energy-efficient communications interface | Andrew Kevin John Stewart, Brian Holden, Amin Shokrollahi | 2016-06-07 |
| 9362974 | Methods and systems for high bandwidth chip-to-chip communications interface | John Fox, Brian Holden, Peter Hunt, John D. Keay, Amin Shokrollahi +3 more | 2016-06-07 |
| 9357036 | Methods and systems for chip-to-chip communication with reduced simultaneous switching noise | John Fox, Brian Holden, Peter Hunt, John D. Keay, Amin Shokrollahi +3 more | 2016-05-31 |
| 9124557 | Methods and systems for chip-to-chip communication with reduced simultaneous switching noise | John Fox, Brian Holden, Peter Hunt, John D. Keay, Amin Shokrollahi +3 more | 2015-09-01 |
| 9106220 | Methods and systems for high bandwidth chip-to-chip communications interface | John Fox, Brian Holden, Peter Hunt, John D. Keay, Amin Shokrollahi +3 more | 2015-08-11 |
| 9071476 | Methods and systems for high bandwidth chip-to-chip communications interface | John Fox, Brian Holden, Ali Hormati, Peter Hunt, John D. Keay +5 more | 2015-06-30 |
| 9059816 | Control loop management and differential delay correction for vector signaling code communications links | Roger Ulrich | 2015-06-16 |
| 8704689 | Method of processing data samples and circuits therefor | Peter Heame | 2014-04-22 |
| 8472580 | Clock recovery | Jonathan Paul Milton, Eugenia Carr Cordero Crespo | 2013-06-25 |
| 7742520 | Equalization circuit | Ruediger Kuhn | 2010-06-22 |
| 7724814 | Methods and apparatus for decision feedback equalization with dithered updating | Eugenia Carr, Mike Harwood | 2010-05-25 |
| 7642938 | Gray code to sign and magnitude converter | — | 2010-01-05 |
| 7315182 | Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control | Robert Floyd Payne, Bhavesh G. Bhakta | 2008-01-01 |
| 7236552 | Data transmission | Iain Robertson, Michael S. Harwood | 2007-06-26 |
| 7233628 | Data transmission | Iain Robertson, Michael S. Harwood, Richard Ward, Andrew Joy, Robert Simpson | 2007-06-19 |
| 7191199 | Method and device for computing an absolute difference | Graeme Swanson, Konstantinos Venos | 2007-03-13 |
| 6986089 | Power reduction in scannable D-flip-flop with synchronous preset or clear | Anthony M. Hill | 2006-01-10 |
| 6839831 | Data processing apparatus with register file bypass | Keith Balmer, Iain Robertson, John D. Keay | 2005-01-04 |
| 6747504 | Controlled rise time output driver | Jonathan Paul Milton, Simon Forey | 2004-06-08 |
| 6614276 | Flip-flop design | Iain Robertson | 2003-09-02 |
| 6532533 | Input/output system with mask register bit control of memory mapped access to individual input/output pins | Amarjit S. Bhandal, Graham B. Short | 2003-03-11 |