Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12316334 | Method and circuit for DLL locking mechanism for wide range harmonic detection and false lock detection | Venkateswara Reddy Pothireddy | 2025-05-27 |
| 12289114 | Methods and apparatus to retime data using a programmable delay | Venkateswara Reddy Pothireddy, Abhijit Kumar Das | 2025-04-29 |
| 12231527 | Clock recovery training | Paul Marion MILLER, IV, Mark Ryan LOVE | 2025-02-18 |
| 12028079 | Methods and apparatus to retime data using a programmable delay | Venkateswara Reddy Pothireddy, Abhijit Kumar Das | 2024-07-02 |
| 9503104 | Low power loss of lock detector | Mustafa Ulvi Erdogan, Sridhar Ramaswamy | 2016-11-22 |
| 8653856 | Electronic device and method for buffering | Oliver Piepenstock, Andreas Bock | 2014-02-18 |
| 7944252 | High performance LVDS driver for scalable supply | Mark W. Morgan | 2011-05-17 |
| 7782932 | Circuit and method for evaluating the performance of an adaptive decision feedback equalizer-based serializer deserializer and serdes incorporating the same | Robert Floyd Payne | 2010-08-24 |
| 7733261 | Hybrid analog to digital converter circuit and method | Vahid Yousefzadeh | 2010-06-08 |
| 7443913 | High speed decision feedback equalizer | Sridhar Ramaswamy, Robert Floyd Payne, Song Wu | 2008-10-28 |
| 7349932 | High performance FIR filter | Sridhar Ramaswamy, Robert Floyd Payne, Song Wu | 2008-03-25 |
| 7315182 | Circuit to observe internal clock and control signals in a receiver with integrated termination and common mode control | Robert Floyd Payne, Richard Simpson | 2008-01-01 |
| 7277828 | Methodology for designing high speed receivers below a target bit-error-rate | Sridhar Ramaswamy, Song Wu | 2007-10-02 |
| 6813111 | Implementation method of digital phase-locked loop | Younggyun Kim | 2004-11-02 |
| 6738206 | Decision error compensation technique for decision-directed timing recovery loop | Younggyun Kim, David Richard Gruetter | 2004-05-18 |
| 6636120 | Decimated digital phase-locked loop for high-speed implementation | Younggyun Kim | 2003-10-21 |
| 6256159 | Method and circuit for dibit detection | — | 2001-07-03 |