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Nitin Agarwal

TI Texas Instruments: 52 patents #128 of 12,488Top 2%
NV NVIDIA: 11 patents #639 of 7,811Top 9%
PS Pentair Water Pool And Spa: 6 patents #21 of 124Top 20%
SS Stmicroelectronics Sa: 6 patents #228 of 1,676Top 15%
IA Infineon Technologies Austria Ag: 4 patents #261 of 1,126Top 25%
QU Qualcomm: 3 patents #4,487 of 12,104Top 40%
HO Honeywell: 2 patents #4,946 of 14,447Top 35%
JL Jio Platforms Limited: 2 patents #34 of 139Top 25%
SN Stmicroelectronics International N.V.: 2 patents #228 of 696Top 35%
PayPal: 1 patents #1,315 of 1,973Top 70%
Microsoft: 1 patents #24,826 of 40,388Top 65%
AS Agere Systems: 1 patents #984 of 1,849Top 55%
SS Stmicroelectronics (Crolles 2) Sas: 1 patents #308 of 529Top 60%
📍 Torrance, CA: #7 of 2,137 inventorsTop 1%
🗺 California: #2,521 of 386,348 inventorsTop 1%
Overall (All Time): #16,286 of 4,157,543Top 1%
94
Patents All Time

Issued Patents All Time

Showing 76–94 of 94 patents

Patent #TitleCo-InventorsDate
8258798 On chip duty cycle measurement module 2012-09-04
8030980 Simplified, extendable, edge-based watchdog for DLL Samarth S. Modi, Mrityunjay Kr. Baranwal 2011-10-04
7804328 Source/emitter follower buffer driving a switching load and having improved linearity Visvesvaraya Pentakota 2010-09-28
7795958 Minimizing changes in common mode voltage at inputs of an operational amplifier used in a switched capacitor differential amplifier Saurabh Singh 2010-09-14
7786909 Analog to digital converter with improved input overload recovery Anand Hariraj Udupa, Neeraj Shrivastava 2010-08-31
7663415 Phase locked loop (PLL) method and architecture Kallol Chatterjee 2010-02-16
7642876 PWM generator providing improved duty cycle resolution 2010-01-05
7598816 Phase lock loop circuit with delaying phase frequency comparson output signals Kallol Chatterjee 2009-10-06
7595744 Correcting offset errors associated with a sub-ADC in pipeline analog to digital converters Ramesh Kumar Singh, Visvesvaraya Pentakota, Dantes John, Supreet Joshi 2009-09-29
7576668 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) Anand Hariraj Udupa, Vikas Sinha, Visvesvararaya A. Pentakota, Sandeep Kesrimal Oswal 2009-08-18
7573414 Maintaining a reference voltage constant against load variations Abhaya Kumar, Visvesvarya Pentakota, Jagannathan Venkataraman 2009-08-11
7479915 Comparator architecture Ramesh Kumar Singh, Abhaya Kumar, Visvesvarya Pentakota A 2009-01-20
7327300 System and method for generating a pulse width modulated signal having variable duty cycle resolution 2008-02-05
7310058 Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC) Anand Hariraj Udupa, Vikas Sinha, Visvesvaraya Pentakota, Sandeep Oswal 2007-12-18
7286003 On-chip voltage regulator Kallol Chatterjee 2007-10-23
7161521 Multi-stage analog to digital converter architecture Gautam Salil Nandi, Visvesvaraya Pentakota, Sandeep Kesrimal Oswal 2007-01-09
7088149 Enhancing SNR and throughput performance of integrated circuits Anand Hariraj Udupa, Visvesvaraya Pentakota, Shakti Shankar Rath, Gautam Salil Nandi, Vineet Mishra +1 more 2006-08-08
6995592 Method and system for generating variable frequency cyclic waveforms using pulse width modulation 2006-02-07
6842136 Low-jitter clock distribution circuit Shakti Shankar Rath 2005-01-11