| 7112532 |
Process for forming a dual damascene structure |
Abbas Ali |
2006-09-26 |
| 6930049 |
Endpoint control for small open area by RF source parameter Vdc |
Jiaming Huang |
2005-08-16 |
| 6803273 |
Method to salicide source-line in flash memory with STI |
Thomas M. Ambrose, Freidoon Mehrad, Lancy Tsung |
2004-10-12 |
| 6605540 |
Process for forming a dual damascene structure |
Abbas Ali |
2003-08-12 |
| 6277720 |
Silicon nitride dopant diffusion barrier in integrated circuits |
Vikram N. Doshi, Takayuki Niuya |
2001-08-21 |
| 6274481 |
Process sequence to improve DRAM data retention |
Jim Huang |
2001-08-14 |
| 5972796 |
In-situ barc and nitride etch process |
Masahiro Kaida, Tom Lassister, Fred Fishburn |
1999-10-26 |
| 5914279 |
Silicon nitride sidewall and top surface layer separating conductors |
Takayuki Niuya |
1999-06-22 |
| 5763020 |
Process for evenly depositing ions using a tilting and rotating platform |
— |
1998-06-09 |
| 5759282 |
Process for evenly depositing ions using a tilting and rotating platform |
— |
1998-06-02 |
| 5554550 |
Method of fabricating electrically eraseable read only memory cell having a trench |
— |
1996-09-10 |
| 5512507 |
Process for post metal coding of a ROM, by gate etch |
Gary Hong |
1996-04-30 |
| 5393702 |
Via sidewall SOG nitridation for via filling |
Hong-Tsz Pan, Shih-Chanh Chang |
1995-02-28 |
| 5264386 |
Read only memory manufacturing method |
— |
1993-11-23 |