Issued Patents All Time
Showing 801–825 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6324662 | TAP and linking module for scan access of multiple cores with IEEE 1149.1 test access ports | Baher Haroun | 2001-11-27 |
| 6304987 | Integrated test circuit | — | 2001-10-16 |
| 6262587 | Semiconductor wafer with connecting leads between the dies | — | 2001-07-17 |
| 6260165 | Accelerating scan test by re-using response data as stimulus data | — | 2001-07-10 |
| 6242269 | Parallel scan distributors and collectors and process of testing integrated circuits | — | 2001-06-05 |
| 6223315 | IP core design supporting user-added scan register option | — | 2001-04-24 |
| 6199182 | Probeless testing of pad buffers on wafer | — | 2001-03-06 |
| 6189115 | Boundary scan input output serializer (BIOS) circuit | — | 2001-02-13 |
| 6166557 | Process of selecting dies for testing on a wafer | — | 2000-12-26 |
| 6158035 | Serial data input/output method and apparatus | Benjamin H. Ashmore, Jr. | 2000-12-05 |
| 6131171 | Process of testing and a process of making circuits | — | 2000-10-10 |
| 6085344 | Data communication interface with memory access controller | Benjamin H. Ashmore, Jr. | 2000-07-04 |
| 6081916 | IC with test cells having separate data and test paths | — | 2000-06-27 |
| 6073254 | Selectively accessing test access ports in a multiple test access port environment | — | 2000-06-06 |
| 6055659 | Boundary scan with latching output buffer and weak input buffer | — | 2000-04-25 |
| 6046600 | Process of testing integrated circuit dies on a wafer | — | 2000-04-04 |
| 6006343 | Method and apparatus for streamlined testing of electrical circuits | — | 1999-12-21 |
| 5994912 | Fault tolerant selection of die on wafer | — | 1999-11-30 |
| 5969538 | Semiconductor wafer with interconnect between dies for testing and a process of testing | — | 1999-10-19 |
| 5938783 | Dual mode memory for IC terminals | — | 1999-08-17 |
| 5905738 | Digital bus monitor integrated circuits | — | 1999-05-18 |
| 5883524 | Low overhead memory designs for IC terminals | — | 1999-03-16 |
| 5880595 | IC having memoried terminals and zero-delay boundary scan | — | 1999-03-09 |
| 5875353 | Circuit with switch controller that signals switch control input to close switch upon completing request acknowledgment of connection request from data transfer port | — | 1999-02-23 |
| 5872908 | IC with isolated analog signal path for testing | — | 1999-02-16 |