Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5410162 | Apparatus for and method of rapid testing of semiconductor components at elevated temperature | Mehrdad M. Moslehi | 1995-04-25 |
| 5407860 | Method of forming air gap dielectric spaces between semiconductor leads | Richard Stoltz, Chih-Chen Cho | 1995-04-18 |
| 5300456 | Metal-to-metal antifuse structure | George R. Misium | 1994-04-05 |
| 5287304 | Memory cell circuit and array | Mark G. Harward, Shivaling S. Mahant-Shetti | 1994-02-15 |
| 5273926 | Method of making flash EEPROM or merged FAMOS cell without alignment sensitivity | — | 1993-12-28 |
| 5262846 | Contact-free floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates | Manzur Gill | 1993-11-16 |
| 5216270 | Non-volatile memory cell with tunnel window structure and method | Cetin Kaya, Mauzur Gill | 1993-06-01 |
| 5200350 | Floating-gate memory array with silicided buried bitlines | Manzur Gill | 1993-04-06 |
| 5159570 | Four memory state EEPROM | Allan T. Mitchell | 1992-10-27 |
| 5130267 | Split metal plate capacitor and method for making the same | Cetin Kaya | 1992-07-14 |
| 5120571 | Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates | Manzur Gill | 1992-06-09 |
| 5108941 | Method of making metal-to-polysilicon capacitor | James L. Paterson | 1992-04-28 |
| 5106773 | Programmable gate array and methods for its fabrication | Cheing-Long Chen, David Kuan-Yu Liu | 1992-04-21 |
| 5095345 | Floating-gate memory array with silicided buried bitlines | Manzur Gill | 1992-03-10 |
| 5084418 | Method of making an array device with buried interconnects | Agerico L. Esquivel, Allan T. Mitchell | 1992-01-28 |
| 5079670 | Metal plate capacitor and method for making the same | James L. Paterson | 1992-01-07 |
| 5065220 | Metal-to-polysilicon capacitor and method for making the same | James L. Paterson | 1991-11-12 |
| 5057886 | Non-volatile memory with improved coupling between gates | Bert R. Riemenschneider | 1991-10-15 |
| 5053839 | Floating gate memory cell and device | Agerico L. Esquivel, Allan T. Mitchell | 1991-10-01 |
| 5045490 | Method of making a pleated floating gate trench EPROM | Agerico L. Esquivel, Allan T. Mitchell | 1991-09-03 |
| 5036020 | Method of fabricating microelectronic device incorporating capacitor having lowered topographical profile | — | 1991-07-30 |
| 5023680 | Floating-gate memory array with silicided buried bitlines and with single-step-defined floating gates | Manzur Gill | 1991-06-11 |
| 5016215 | High speed EPROM with reverse polarity voltages applied to source and drain regions during reading and writing | — | 1991-05-14 |
| 4997781 | Method of making planarized EPROM array | — | 1991-03-05 |
| 4979004 | Floating gate memory cell and device | Agerico L. Esquivel, Allan T. Mitchell | 1990-12-18 |