Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10056911 | Continuous coarse-tuned phase locked loop | — | 2018-08-21 |
| 9356570 | High speed, rail-to-rail CMOS differential input stage | — | 2016-05-31 |
| 8166286 | Data pipeline with large tuning range of clock signals | Ingolf Frank | 2012-04-24 |
| 8111092 | Register with process, supply voltage and temperature variation independent propagation delay path | Sotirios Tambouris | 2012-02-07 |
| 7868670 | Phase-locked loop (PLL) circuit and method | Georg Becke | 2011-01-11 |
| 7800975 | Digital data buffer with phase aligner | Soritios Tambouris | 2010-09-21 |
| 7663417 | Phase-locked loop circuit | — | 2010-02-16 |
| 7154345 | PLL circuit having reduced capacitor size | Miki Moyal | 2006-12-26 |
| 6590458 | Clock generator circuit with a PLL having an output frequency cycled in a range to reduce unwanted radiation | Hermann Seibold | 2003-07-08 |
| 6154089 | Fast bus driver with reduced standby power consumption | — | 2000-11-28 |
| 5852383 | Control circuit for bicmos bus drivers | — | 1998-12-22 |