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Simplified LDPC encoding for digital communications |
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Parity check decoder architecture |
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Layered decoding of low density parity check (LDPC) codes |
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Hardware-efficient low density parity check code for digital communications |
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Encoding for digital communications in a multiple-input, multiple-output environment |
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2010-02-23 |
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High-performance LDPC coding for digital communications in a multiple-input, multiple-output environment |
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2010-02-23 |
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Simplified decoding using structured and punctured LDPC codes |
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2009-08-25 |
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Simplified LDPC encoding for digital communications |
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Layered decoding approach for low density parity check (LDPC) codes |
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2007-02-20 |
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Hardware-efficient low density parity check code for digital communications |
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2007-02-13 |
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Efficient encoder for low-density-parity-check codes |
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2007-01-09 |
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Layered low density parity check decoding for digital communications |
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2006-11-21 |
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Computing the full path metric in viterbi decoding |
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2005-08-23 |
| 6901118 |
Enhanced viterbi decoder for wireless applications |
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2005-05-31 |
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Flexible Viterbi decoder for wireless applications |
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2004-02-10 |
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Reconfigurable multiply-accumulate hardware co-processor unit |
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2001-10-02 |
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Digital signal processor with efficiently connectable hardware co-processor |
Alan Gatherer, Carl E. Lemonds, Ching-Yu Hung |
2001-07-03 |
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Method and apparatus for storing decoded video information |
Yetung Paul Chiang |
1999-12-14 |