Issued Patents All Time
Showing 25 most recent of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12204475 | Using a hardware sequencer in a direct memory access system of a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2025-01-21 |
| 12118353 | Performing load and permute with a single instruction in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2024-10-15 |
| 12099439 | Performing load and store operations of 2D arrays in a single cycle in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2024-09-24 |
| 12093539 | Using per memory bank load caches for reducing power use in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2024-09-17 |
| 12050548 | Built-in self-test for a programmable vision accelerator of a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2024-07-30 |
| 11954496 | Reduced memory write requirements in a system on a chip using automatic store predication | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2024-04-09 |
| 11940947 | Hardware accelerated anomaly detection using a min/max collector in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2024-03-26 |
| 11934829 | Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2024-03-19 |
| 11836527 | Accelerating table lookups using a decoupled lookup table accelerator in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Ahmad Itani, Yen-Te Shih | 2023-12-05 |
| 11704067 | Performing multiple point table lookups in a single cycle in a system on chip | Ravi P. Singh, Jagadeesh Sankaran, Ahmad Itani, Yen-Te Shih | 2023-07-18 |
| 11636063 | Hardware accelerated anomaly detection using a min/max collector in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2023-04-25 |
| 11630800 | Programmable vision accelerator | Jagadeesh Sankaran, Ravi P. Singh, Stanley Tzeng | 2023-04-18 |
| 11593001 | Using per memory bank load caches for reducing power use in a system on a chip | Ravi P. Singh, Jagadeesh Sankaran, Yen-Te Shih, Ahmad Itani | 2023-02-28 |
| 11593290 | Using a hardware sequencer in a direct memory access system of a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2023-02-28 |
| 11573921 | Built-in self-test for a programmable vision accelerator of a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2023-02-07 |
| 11573795 | Using a vector processor to configure a direct memory access system for feature tracking operations in a system on a chip | Ahmad Itani, Yen-Te Shih, Jagadeesh Sankaran, Ravi P. Singh | 2023-02-07 |
| 11468003 | Vector table load instruction with address generation field to access table offset value | Shinri Inamori, Jagadeesh Sankaran, Peter Chang | 2022-10-11 |
| 10803009 | Processor with table lookup processing unit | Shinri Inamori, Jagadeesh Sankaran, Peter Chang | 2020-10-13 |
| 9519617 | Processor with instruction variable data distribution | Shinri Inamori, Jagadeesh Sankaran, Peter Chang | 2016-12-13 |
| 9092228 | Systems and methods for software instruction translation from a high-level language to a specialized instruction set | Alan L. Davis, Jadadeesh Sankaran, James Nagurne, Mel Alan Phipps, Ajay Jayaraj | 2015-07-28 |
| 8619866 | Reducing memory bandwidth for processing digital image data | Minhua Zhou | 2013-12-31 |
| 8111760 | Deblocking filters | Ngai-Man Cheung | 2012-02-07 |
| 7797362 | Parallel architecture for matrix transposition | Nara Won | 2010-09-14 |
| 7728840 | Sliding data buffering for image processing | — | 2010-06-01 |
| 7593580 | Video encoding using parallel processors | Damon Domke, Youngjun Yoo, Deependra Talla | 2009-09-22 |