Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5143860 | High density EPROM fabricaiton method having sidewall floating gates | Bert R. Riemenschneider, Howard L. Tigilaar | 1992-09-01 |
| 5120672 | Fabricating a single level merged EEPROM cell having an ONO memory stack substantially spaced from the source region | Bert R. Riemenschneider | 1992-06-09 |
| 5114530 | Interlevel dielectric process | Kalipatnam Vivek Rao, James L. Paterson | 1992-05-19 |
| 5105245 | Trench capacitor DRAM cell with diffused bit lines adjacent to a trench | Bert R. Riemenschneider, Clarence W. Teng | 1992-04-14 |
| 5084418 | Method of making an array device with buried interconnects | Agerico L. Esquivel, Howard L. Tigelaar | 1992-01-28 |
| 5053839 | Floating gate memory cell and device | Agerico L. Esquivel, Howard L. Tigelaar | 1991-10-01 |
| 5045490 | Method of making a pleated floating gate trench EPROM | Agerico L. Esquivel, Howard L. Tigelaar | 1991-09-03 |
| 5036375 | Floating-gate memory cell with tailored doping profile | — | 1991-07-30 |
| 5028553 | Method of making fast, trench isolated, planar flash EEPROMS with silicided bitlines | Agerico L. Esquivel | 1991-07-02 |
| 4980309 | Method of making high density EEPROM | Bert R. Riemenschneider | 1990-12-25 |
| 4979005 | Floating-gate memory cell with tailored doping profile | — | 1990-12-18 |
| 4979004 | Floating gate memory cell and device | Agerico L. Esquivel, Howard L. Tigelaar | 1990-12-18 |
| 4977439 | Buried multilevel interconnect system | Agerico L. Esquivel | 1990-12-11 |
| 4951103 | Fast, trench isolated, planar flash EEPROMS with silicided bitlines | Agerico L. Esquivel | 1990-08-21 |
| 4905062 | Planar famos transistor with trench isolation | Agerico L. Esquivel | 1990-02-27 |
| 4878996 | Method for reduction of filaments between electrodes | Howard L. Tigelaar, Shaym G. Garg, Kalipatnam Vivek Rao | 1989-11-07 |
| 4853895 | EEPROM including programming electrode extending through the control gate electrode | Bert R. Riemenschneider | 1989-08-01 |
| 4839705 | X-cell EEPROM array | Howard L. Tigelaar, Bert R. Riemenschneider, James L. Paterson | 1989-06-13 |
| 4833514 | Planar FAMOS transistor with sealed floating gate and DCS+N.sub.2 O oxide | Agerico L. Esquivel | 1989-05-23 |
| 4829019 | Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment | Howard L. Tigelaar, Bert R. Riemenschneider | 1989-05-09 |
| 4806201 | Use of sidewall oxide to reduce filaments | Howard L. Tigelaar, Shaym G. Garg, Kalipatnam Vivek Rao | 1989-02-21 |
| 4799992 | Interlevel dielectric fabrication process | Kalipatnam Vivek Rao, James L. Paterson | 1989-01-24 |
| 4749443 | Sidewall oxide to reduce filaments | Howard L. Tigelaar | 1988-06-07 |
| 4713142 | Method for fabricating EPROM array | James L. Paterson | 1987-12-15 |
| 4597060 | EPROM array and method for fabricating | James L. Paterson | 1986-06-24 |