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Ashish B. Dixit

TE Tensilica: 5 patents #11 of 43Top 30%
SG Silicon Graphics: 3 patents #134 of 758Top 20%
IN Intel: 3 patents #10,349 of 30,777Top 35%
CS Cadence Design Systems: 2 patents #781 of 2,263Top 35%
📍 Fremont, CA: #1,349 of 9,298 inventorsTop 15%
🗺 California: #46,935 of 386,348 inventorsTop 15%
Overall (All Time): #384,760 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
8924898 System and method of designing instruction extensions to supplement an existing processor instruction set architecture Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2014-12-30
8875068 System and method of customizing an existing processor design having an existing processor instruction set architecture with instruction extensions Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2014-10-28
8006204 Automated processor generation system for designing a configurable processor and method for the same Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2011-08-23
7020854 Automated processor generation system for designing a configurable processor and method for the same Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2006-03-28
6760888 Automated processor generation system for designing a configurable processor and method for the same Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2004-07-06
6477683 Automated processor generation system for designing a configurable processor and method for the same Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +4 more 2002-11-05
6282633 High data density RISC processor Earl A. Killian, Ricardo E. Gonzalez, Monica Lam, Walter D. Lichtenstein, Christopher Rowen +2 more 2001-08-28
5574877 TLB with two physical pages per virtual tag Earl A. Killian 1996-11-12
5568630 Backward-compatible computer architecture with extended word size and address space Earl A. Killian, Thomas J. Riordan, Danny L. Freitas, John L. Hennessy 1996-10-22
5420992 Backward-compatible computer architecture with extended word size and address space Earl A. Killian, Thomas J. Riordan, Danny L. Freitas, John L. Hennessy 1995-05-30
5408626 One clock address pipelining in segmentation unit 1995-04-18
5204953 One clock address pipelining in segmentation unit 1993-04-20
5201043 System using both a supervisor level control bit and a user level control bit to enable/disable memory reference alignment checking John H. Crawford 1993-04-06