Issued Patents All Time
Showing 176–200 of 227 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7943967 | Semiconductor device and associated layouts including diffusion contact placement restriction based on relation to linear conductive segments | Michael C. Smayling | 2011-05-17 |
| 7939898 | Diffusion variability control and transistor device sizing using threshold voltage implant | Michael C. Smayling | 2011-05-10 |
| 7939443 | Methods for multi-wire routing and apparatus implementing same | Daryl Fox | 2011-05-10 |
| 7932544 | Semiconductor device and associated layouts including linear conductive segments having non-gate extension portions | Michael C. Smayling | 2011-04-26 |
| 7932545 | Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers | Michael C. Smayling | 2011-04-26 |
| 7923757 | Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level | Michael C. Smayling | 2011-04-12 |
| 7917879 | Semiconductor device with dynamic array section | Michael C. Smayling | 2011-03-29 |
| 7917885 | Methods for creating primitive constructed standard cells | — | 2011-03-29 |
| 7910958 | Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment | Michael C. Smayling | 2011-03-22 |
| 7910959 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode connection through single interconnect level | Michael C. Smayling | 2011-03-22 |
| 7908578 | Methods for designing semiconductor device with dynamic array section | Michael C. Smayling | 2011-03-15 |
| 7906801 | Semiconductor device and associated layouts having transistors formed from six linear conductive segments with intervening diffusion contact restrictions | Michael C. Smayling | 2011-03-15 |
| 7888705 | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same | Michael C. Smayling | 2011-02-15 |
| 7842975 | Dynamic array architecture | Michael C. Smayling | 2010-11-30 |
| 7763534 | Methods, structures and designs for self-aligning local interconnects used in integrated circuits | Michael C. Smayling | 2010-07-27 |
| 7590968 | Methods for risk-informed chip layout generation | Michael C. Smayling | 2009-09-15 |
| 7446352 | Dynamic array architecture | Michael C. Smayling | 2008-11-04 |
| 7343581 | Methods for creating primitive constructed standard cells | — | 2008-03-11 |
| 7005910 | Feed-forward circuit for reducing delay through an input buffer | Brian Reed, Puneet Sawhney, Jayanth Thyamagundlam | 2006-02-28 |
| 6944582 | Methods for reducing bitline voltage offsets in memory devices | — | 2005-09-13 |
| 6934213 | Method and apparatus for reducing write power consumption in random access memories | — | 2005-08-23 |
| 6924687 | Voltage tolerant circuit for protecting an input buffer | Brian Reed, Puneet Sawhney, Jayanth Thyamagundlam | 2005-08-02 |
| 6915251 | Memories having reduced bitline voltage offsets | — | 2005-07-05 |
| 6865119 | Negatively charged wordline for reduced subthreshold current | — | 2005-03-08 |
| 6833624 | System and method for row decode in a multiport memory | — | 2004-12-21 |