YL

Yai-Fen Lin

TSMC: 67 patents #463 of 12,232Top 4%
Overall (All Time): #32,146 of 4,157,543Top 1%
67
Patents All Time

Issued Patents All Time

Showing 26–50 of 67 patents

Patent #TitleCo-InventorsDate
6333228 Method to improve the control of bird's beak profile of poly in split gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh, Wen-Ting Chu, Di-Son Kuo 2001-12-25
6326660 Method to improve the capacity of data retention and increase the coupling ratio of source to floating gate in split-gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo 2001-12-04
6312989 Structure with protruding source in split-gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Wen-Ting Chu, Di-Son Kuo 2001-11-06
6309928 Split-gate flash cell Hung-Cheng Sung, Di-Son Kuo, Chuang-Ke Yeh, Chia-Ta Hsieh, Wen-Ting Chu 2001-10-30
6277686 PIP capacitor for split-gate flash process Chung-Ker Yeh, Hung-Cheng Sung, Di-Son Kuo, Chia-Ta Hsieh 2001-08-21
6259131 Poly tip and self aligned source for split-gate flash cell Hung-Cheng Sung, Di-Son Kou, Chia-Ta Hsieh 2001-07-10
6249454 Split-gate flash cell for virtual ground architecture Hung-Cheng Sung, Di-Son Kuo, Chia-Ta Hsieh 2001-06-19
6246089 P-channel EEPROM devices Shiou-Hann Liaw, Di-Son Kuo, Juang-Ke Yeh 2001-06-12
6242308 Method of forming poly tip to improve erasing and programming speed split gate flash Chia-Ta Hsieh, Di-Son Kuo, Hung-Cheng Sung 2001-06-05
6228695 Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh, Di-Son Kuo 2001-05-08
6229176 Split gate flash with step poly to improve program speed Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo 2001-05-08
6214662 Forming self-align source line for memory array Hung-Cheng Sung, Di-Son Kuo, Chia-Ta Hsieh 2001-04-10
6207515 Method of fabricating buried source to shrink chip size in memory array Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Hung-Cheng Sung 2001-03-27
6207503 Method for shrinking array dimensions of split gate flash memory device using multilayer etching to define cell and source line Chia-Ta Hsieh, Hung-Cheng Sung, Di-Son Kuo 2001-03-27
6188103 Method of forming sharp beak of poly by nitrogen implant to improve erase speed for split-gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Di-Son Kuo 2001-02-13
6180977 Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash Hung-Cheng Sung, Chia-Ta Hsieh, Di-Son Kuo 2001-01-30
6174772 Optimal process flow of fabricating nitride spacer without inter-poly oxide damage in split gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh, Di-Son Kuo 2001-01-16
6171906 Method of forming sharp beak of poly to improve erase speed in split gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Chuang-Ke Yeh, Di-Son Kuo 2001-01-09
6165845 Method to fabricate poly tip in split-gate flash Chia-Ta Hsieh, Hung-Cheng Sung, Jack Y. Yeh, Di-Son Kuo 2000-12-26
6159801 Method to increase coupling ratio of source to floating gate in split-gate flash Chia-Ta Hsieh, Di-Son Kuo, Hung-Cheng Sung, Jack Y. Yeh 2000-12-12
6153494 Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash Chia-Ta Hsieh, Di-Son Kuo, Chrong-Jung Lin, Jong Chen, Hung-Der Su 2000-11-28
6130132 Clean process for manufacturing of split-gate flash memory device having floating gate electrode with sharp peak Chia-Ta Hsieh, Hung-Cheng Sung, Di-Son Kuo 2000-10-10
6127229 Process of forming an EEPROM device having a split gate Wen-Ting Chu, Di-Son Kuo, Hung-Cheng Sung, Jack Y. Yeh, Chia-Ta Hsieh 2000-10-03
6124609 Split gate flash memory with buried source to shrink cell dimension and increase coupling ratio Chia-Ta Hsieh, Jenn Tsao, Di-Son Kuo, Hung-Cheng Sung 2000-09-26
6121088 Method of manufacture of undoped polysilicon as the floating-gate of a split-gate flash cell Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh, Di-Son Kuo 2000-09-19