Issued Patents All Time
Showing 51–70 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11615962 | Semiconductor structures and methods thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-03-28 |
| 11600533 | Semiconductor device fabrication methods and structures thereof | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Kuan-Lun Cheng +1 more | 2023-03-07 |
| 11594614 | P-metal gate first gate replacement process for multigate devices | Jia-Ni Yu, Kuo-Cheng Chiang, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang | 2023-02-28 |
| 11563109 | Semiconductor device structure and method for forming the same | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Chun-Fu Lu, Kuo-Cheng Chiang +2 more | 2023-01-24 |
| 11502168 | Tuning threshold voltage in nanosheet transitor devices | Chung-Wei Hsu, Hou-Yu Chen, Chih-Hao Wang, Ching-Wei Tsai, Kuo-Cheng Chiang +3 more | 2022-11-15 |
| 11450664 | Semiconductor device having nanosheet transistor and methods of fabrication thereof | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Kuan-Lun Cheng +1 more | 2022-09-20 |
| 11417653 | Semiconductor structure and method for forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang | 2022-08-16 |
| 11387346 | Gate patterning process for multi-gate devices | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-07-12 |
| 11374105 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang | 2022-06-28 |
| 11264288 | Gate structure and patterning method | Mao-Lin Huang, Wei-Hao Wu, Kuo-Cheng Chiang | 2022-03-01 |
| 11257815 | Work function design to increase density of nanosheet devices | Mao-Lin Huang, Chih-Hao Wang, Kuo-Cheng Chiang, Jia-Ni Yu, Chung-Wei Hsu | 2022-02-22 |
| 11244871 | Methods of fabricating semiconductor devices for tightening spacing between nanosheets in GAA structures and structures formed thereby | Kuo-Cheng Chiang, Chung-Wei Hsu, Mao-Lin Huang, Jia-Ni Yu, Chih-Hao Wang | 2022-02-08 |
| 11205650 | Input/output semiconductor devices | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2021-12-21 |
| 11201094 | Forming metal gates with multiple threshold voltages | Mao-Lin Huang, Wei-Hao Wu | 2021-12-14 |
| 11152477 | Transistors with different threshold voltages | Mao-Lin Huang, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang, Chih-Hao Wang | 2021-10-19 |
| 11145734 | Semiconductor device with dummy fin and liner and method of forming the same | Jia-Ni Yu, Kuo-Cheng Chiang, Mao-Lin Huang, Chung-Wei Hsu, Chih-Hao Wang +1 more | 2021-10-12 |
| 11024545 | Semiconductor arrangement and method of manufacture | Kuo-Cheng Ching, Mao-Lin Huang, Chung-Wei Hsu | 2021-06-01 |
| 10937704 | Mixed workfunction metal for nanosheet device | Kuo-Cheng Chiang, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang, Mao-Lin Huang | 2021-03-02 |
| 10867867 | Methods of fabricating semiconductor devices with mixed threshold voltages boundary isolation of multiple gates and structures formed thereby | Kuo-Cheng Chiang, Chung-Wei Hsu, Jia-Ni Yu, Chih-Hao Wang, Mao-Lin Huang | 2020-12-15 |
| 9960085 | Multiple patterning techniques for metal gate | Hsiang-Pi Chang, Chih-Hao Wang, Wei-Hao Wu, Hung-Chang Sun | 2018-05-01 |