Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11233121 | Method of making bipolar transistor | Fu-Hsiung Yang, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu | 2022-01-25 |
| 11056406 | Stack of multiple deposited semiconductor layers | Liyan Miao, Chentsau Ying, Xinhai Han | 2021-07-06 |
| 10686036 | Method of making bipolar transistor | Fu-Hsiung Yang, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu | 2020-06-16 |
| 10490467 | Methods of forming a stack of multiple deposited semiconductor layers | Liyan Miao, Chentsau Ying, Xinhai Han | 2019-11-26 |
| 10002761 | Method for forming a multiple layer epitaxial layer on a wafer | Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu | 2018-06-19 |
| 9853121 | Method of fabricating a lateral insulated gate bipolar transistor | Kun-Ming Huang, Ming-Yi Lin | 2017-12-26 |
| 9698024 | Partial SOI on power device for breakdown voltage improvement | Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu | 2017-07-04 |
| 9647065 | Bipolar transistor structure having split collector region and method of making the same | Fu-Hsiung Yang, Kun-Ming Huang, Chih-Heng Shen, Po-Tao Chu | 2017-05-09 |
| 9111898 | Multiple layer substrate | Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Paul Chu | 2015-08-18 |
| 9076837 | Lateral insulated gate bipolar transistor structure with low parasitic BJT gain and stable threshold voltage | Kun-Ming Huang, Ming-Yi Lin | 2015-07-07 |
| 8779555 | Partial SOI on power device for breakdown voltage improvement | Fu-Hsiung Yang, Kun-Ming Huang, Ming-Yi Lin, Po-Tao Chu | 2014-07-15 |
| 8125008 | Schottky device and process of making the same comprising a geometry gap | Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu | 2012-02-28 |
| 7732890 | Integrated circuit with high voltage junction structure | Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu | 2010-06-08 |
| 7655990 | Voltage-clipping device with high breakdown voltage | Chiu-Chih Chiang, Chih-Feng Huang, You-Kuo Wu | 2010-02-02 |