Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12063360 | Prediction processing system using reference data buffer to achieve parallel non-inter and inter prediction and associated prediction processing method | Chi-Hung Chen, Meng Hu, Hsiao-En Chen, Chih-Wen Yang, Chien-Wei Lin | 2024-08-13 |
| 11800122 | Video processing apparatus using internal prediction buffer that is shared by multiple coding tools for prediction | Chih-Wen Yang, Chi-Hung Chen, Chien-Wei Lin, Meng Hu | 2023-10-24 |
| 11119416 | Method for forming semiconductor structure and overlay error estimation | Che-Yuan Sun, Yen-Liang Chen, He Fan, Yen-Hung Chen | 2021-09-14 |
| 10939102 | Post processing apparatus with super-resolution filter and loop restoration filter in block-level pipeline and associated post processing method | Yung-Chang Chang, Chih-Ming Wang, Chia-Yun Cheng, Chi-Hung Chen, Chih-Wen Yang +1 more | 2021-03-02 |
| 10714535 | Resistive memory array and fabricating method thereof | Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih | 2020-07-14 |
| 10372948 | Scrambling apparatus and method thereof | Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih | 2019-08-06 |
| 10281942 | Low-dropout regulator | Yuan-Long Siao, Ku-Feng Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih | 2019-05-07 |
| 10163980 | Resistive memory array and fabricating method thereof | Ku-Feng Lin, Hung-Chang Yu, Yu-Der Chih | 2018-12-25 |
| 9910451 | Low-dropout regulator | Yuan-Long Siao, Ku-Feng Lin, Hung-Chang Yu, Chia-Fu Lee, Yue-Der Chih | 2018-03-06 |
| 9865601 | Semiconductor integrated circuit | Yu-Der Chih, Chia-Fu Lee | 2018-01-09 |
| 9806064 | Package with multiple plane I/O structure | Hung-Chang Yu, Yue-Der Chih | 2017-10-31 |
| 9747159 | MRAM smart bit write algorithm with error correction parity bits | Yue-Der Chih, Hung-Chang Yu, Chin-Yi Huang, Laun C. Tran | 2017-08-29 |
| 9742497 | Semiconductor arrangement and formation thereof | Hung-Chang Yu, Yu-Der Chih, Ying-Hao Kuo | 2017-08-22 |
| 9711190 | Stabilizing circuit | Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih | 2017-07-18 |
| 9413140 | Semiconductor arrangement and formation thereof | Hung-Chang Yu, Ying-Hao Kuo, Yue-Der Chih | 2016-08-09 |
| 9406367 | Method and apparatus for MRAM sense reference trimming | Yue-Der Chih, Hung-Chang Yu | 2016-08-02 |
| 9368552 | Resistive memory array and fabricating method thereof | Ku-Feng Lin, Hung-Chang Yu, Yue-Der Chih | 2016-06-14 |
| 9330746 | Resistive memory array | Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih | 2016-05-03 |
| 9299677 | Package with multiple plane I/O structure | Hung-Chang Yu, Yue-Der Chih | 2016-03-29 |
| 9165629 | Method and apparatus for MRAM sense reference trimming | Yue-Der Chih, Hung-Chang Yu | 2015-10-20 |
| 9110829 | MRAM smart bit write algorithm with error correction parity bits | Yue-Der Chih, Hung-Chang Yu, Chin-Yi Huang, Laun C. Tran | 2015-08-18 |
| 9058872 | Resistance-based random access memory | Hung-Chang Yu, Yue-Der Chih | 2015-06-16 |
| 8964458 | Differential MRAM structure with relatively reversed magnetic tunnel junction elements enabling writing using same polarity current | Hung-Chang Yu, Yue-Der Chih, Chun-Jung Lin | 2015-02-24 |
| 8923040 | Accommodating balance of bit line and source line resistances in magnetoresistive random access memory | Hung-Chang Yu, Ku-Feng Lin, Yue-Der Chih | 2014-12-30 |
| 8908439 | Adaptive word-line boost driver | Ku-Feng Lin, Hung-Chang Yu | 2014-12-09 |