Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12230603 | Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer | Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Yu Lee | 2025-02-18 |
| 12142574 | Semiconductor devices and methods of manufacture | Yao-Te Huang, Yung-Shih Cheng, Jiing-Feng Yang, Hui Yu Lee | 2024-11-12 |
| 12094930 | Integrated circuit structure and method for forming the same | Guan-Yao Tu, Su-Jen Sung, Tze-Liang Lee | 2024-09-17 |
| 12074107 | Structure and method of forming a semiconductor device with resistive elements | Yung-Shih Cheng, Wen-Sheh Huang | 2024-08-27 |
| 11923295 | Interconnect level with high resistance layer and method of forming the same | Yung-Shih Cheng, Wen-Sheh Huang, Yu-Hsiang Chen | 2024-03-05 |
| 11908829 | Integrated circuit package and method of forming same | Yao-Te Huang, Yung-Shih Cheng | 2024-02-20 |
| 11756924 | Method of fabricating a semiconductor chip having strength adjustment pattern in bonding layer | Jiing-Feng Yang, Yung-Shih Cheng, Yao-Te Huang, Hui Yu Lee | 2023-09-12 |
| 11437313 | Structure and method of forming a semiconductor device with resistive elements | Yung-Shih Cheng, Wen-Sheh Huang | 2022-09-06 |