Issued Patents All Time
Showing 26–35 of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10922470 | Method and system of forming semiconductor device | Kuo-Nan Yang, Wan-Yu Lo, Chung-Hsing Wang | 2021-02-16 |
| 10878163 | Semiconductor device including PG-aligned cells and method of generating layout of same | Chung-Hsing Wang, Kuo-Nan Yang | 2020-12-29 |
| 10867103 | Method and system for forming conductive grid of integrated circuit | Kuo-Nan Yang, Chung-Hsing Wang | 2020-12-15 |
| 10867916 | Via sizing for IR drop reduction | Chin-Shen Lin, Kuo-Nan Yang, Chung-Hsing Wang | 2020-12-15 |
| 10672709 | Power grid, IC and method for placing power grid | Kuo-Nan Yang, Chung-Hsing Wang | 2020-06-02 |
| 10664641 | Integrated device and method of forming the same | Kuo-Nan Yang, Chung-Hsing Wang, Meng-Xiang Lee | 2020-05-26 |
| 10515178 | Merged pillar structures and method of generating layout diagram of same | Chung-Hsing Wang, Kuo-Nan Yang, Yi-Kan Cheng | 2019-12-24 |
| 10515944 | Integrated circuit and method of generating integrated circuit layout | Fong-Yuan Chang, Kuo-Nan Yang, Chung-Hsing Wang, Lee-Chung Lu, Sheng-Fong Chen +3 more | 2019-12-24 |
| 10509888 | System and method for forming integrated device | Kuo-Nan Yang, Chung-Hsing Wang | 2019-12-17 |
| 10360337 | Method of forming conductive grid of integrated circuit | Kuo-Nan Yang, Chung-Hsing Wang | 2019-07-23 |