Issued Patents All Time
Showing 76–100 of 229 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12107022 | Systems and methods of testing memory devices | Meng-Han Lin | 2024-10-01 |
| 12101938 | Semiconductor memory devices and methods of manufacturing thereof | Meng-Han Lin | 2024-09-24 |
| 12100673 | Chemical mechanical polishing dishing resistant structure | Meng-Han Lin | 2024-09-24 |
| 12089417 | Semiconductor memory devices and methods of manufacturing thereof | Meng-Han Lin | 2024-09-10 |
| 12089414 | Memory device and method of forming the same | Bo-Feng Young, Sai-Hooi Yeong, Shih-Lien Linus Lu, Yih Wang, Yu-Ming Lin | 2024-09-10 |
| 12089402 | Integrated circuit layout and method | Meng-Sheng Chang, Chien-Ying Chen, Yih Wang | 2024-09-10 |
| 12087354 | Memory device | Tzu-Hsien Yang, Yih Wang, Jonathan Tsung-Yung Chang | 2024-09-10 |
| 12087345 | Balanced negative bitline voltage for a write assist circuit | Jui-Che Tsai, Chia-Cheng Chen, Yih Wang | 2024-09-10 |
| 12080641 | Electrical fuse bit cell in integrated circuit having backside conducting lines | Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Meng-Sheng Chang | 2024-09-03 |
| 12079152 | Systems and methods of testing memory devices | Meng-Han Lin | 2024-09-03 |
| 12075614 | MIM memory cell with backside interconnect structures | Meng-Sheng Chang, Yih Wang | 2024-08-27 |
| 12069862 | Semiconductor dies including low and high workfunction semiconductor devices | Meng-Han Lin | 2024-08-20 |
| 12068377 | Back-end-of-line devices | Yu-Hsiang Chen, Po-Hsiang Huang, Wen-Sheh Huang, Hsing-Leo Tsai | 2024-08-20 |
| 12068263 | Semiconductor memory devices and methods of manufacturing thereof | Meng-Han Lin | 2024-08-20 |
| 12068023 | Memory circuits, memory structures, and methods for fabricating a memory device | Chieh Lee, Yi-Ching Liu, Wen-Chang Cheng, Jonathan Tsung-Yung Chang | 2024-08-20 |
| 12063786 | Compute-in-memory device and method | Chieh Lee, Yi-Ching Liu, Wen-Chang Cheng, Yih Wang | 2024-08-13 |
| 12063773 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-08-13 |
| 12062408 | Switches to reduce routing rails of memory system | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2024-08-13 |
| 12058868 | Semiconductor memory devices with arrays of vias and methods of manufacturing thereof | Meng-Han Lin | 2024-08-06 |
| 12052859 | Non-volatile memory device with reduced area | Meng-Sheng Chang, Yao-Jen Yang, Yih Wang | 2024-07-30 |
| 12051464 | Semiconductor memory devices with different word lines | Meng-Sheng Chang, Gu-Huan Li | 2024-07-30 |
| 12048147 | Layout structure including anti-fuse cell | Meng-Sheng Chang, Wan-Hsueh Cheng, Yao-Jen Yang, Yih Wang | 2024-07-23 |
| 12029042 | 3D memory device with modulated doped channel | Peng-Chun Liou, Zhiqiang Wu, Chung-Wei Wu, Yi-Ching Liu | 2024-07-02 |
| 12027204 | Memory including metal rails with balanced loading | Meng-Sheng Chang, Yi-Ching Liu, Yih Wang | 2024-07-02 |
| 12020996 | Systems and methods of testing memory devices | Meng-Han Lin | 2024-06-25 |