Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10163883 | Layout method for integrated circuit and layout of the integrated circuit | Cheok-Kei Lei, Yu Li, Chia-Wei Tseng, Zhe-Wei Jiang, Jerry Chang Jui Kao +3 more | 2018-12-25 |
| 10003342 | Compressor circuit and compressor circuit layout | Lee-Chung Lu, Meng Wang, Shang-Chih Hsieh, Henry Huang, Ji-Yung LIN | 2018-06-19 |
| 9887698 | Internal clock gated cell | Lee-Chung Lu, Shang-Chih Hsieh | 2018-02-06 |
| 9853630 | Skew-tolerant flip-flop | Jerry Chang Jui Kao, Lee-Chung Lu, Shang-Chih Hsieh, Bor-Tyng Lin | 2017-12-26 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Shang-Chih Hsieh +1 more | 2017-05-02 |
| 9584099 | Flip flop circuit | Shang-Chih Hsieh, Lee-Chung Lu, Chang-Yu Wu | 2017-02-28 |
| 9356583 | Flip-flop circuit | Shang-Chih Hsieh, Lee-Chung Lu, Chang-Yu Wu | 2016-05-31 |
| 9203405 | Low-power internal clock gated cell and method | Shang-Chih Hsieh, Lee-Chung Lu, Meng Wang, Chang-Yu Wu | 2015-12-01 |
| 8575965 | Internal clock gating apparatus | Chung-Cheng Chou, Yangsyu Lin, Hsiao Wen Lu | 2013-11-05 |
| 8416002 | Flip-flop circuit design | Chung-Cheng Chou, Yi-Tzu Chen | 2013-04-09 |
| 8359528 | Parity look-ahead scheme for tag cache memory | Yi-Tzu Chen, Chung-Cheng Chou | 2013-01-22 |