Patent Leaderboard
USPTO Patent Rankings Data through Sept 30, 2025
AR

Andre Rohe

TATabula: 20 patents #6 of 42Top 15%
Google: 18 patents #1,160 of 22,993Top 6%
IBM: 1 patents #44,794 of 70,183Top 65%
Mountain View, CA: #345 of 11,022 inventorsTop 4%
California: #10,539 of 386,348 inventorsTop 3%
Overall (All Time): #73,413 of 4,157,543Top 2%
42 Patents All Time

Issued Patents All Time

Showing 26–42 of 42 patents

Patent #TitleCo-InventorsDate
7898291 Operational time extension Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell 2011-03-01
7870529 Operational cycle assignment in a configurable IC Steven Teig 2011-01-11
7870530 Operational cycle assignment in a configurable IC Steven Teig 2011-01-11
7849434 Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Steven Teig 2010-12-07
7737722 Configurable integrated circuit with built-in turns Steven Teig 2010-06-15
7694265 Operational cycle assignment in a configurable IC Steven Teig 2010-04-06
7587698 Operational time extension Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell 2009-09-08
7557609 Configurable integrated circuit with different connection schemes Steven Teig 2009-07-07
7496879 Concurrent optimization of physical design and operational cycle assignment Steven Teig 2009-02-24
7468614 Configurable integrated circuit with offset connections Steven Teig 2008-12-23
7428721 Operational cycle assignment in a configurable IC Steven Teig 2008-09-23
7312630 Configurable integrated circuit with built-in turns Steven Teig 2007-12-25
7284222 Method and apparatus for identifying connections between configurable nodes in a configurable integrated circuit Steven Teig 2007-10-16
7236009 Operational time extension Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell 2007-06-26
7193438 Configurable integrated circuit with offset connection Steven Teig 2007-03-20
7145361 Configurable integrated circuit with different connection schemes Steven Teig 2006-12-05
6904584 Method and system for placing logic nodes based on an estimated wiring congestion Ulrich Brenner, Philip S. Honsinger, Juergen Koehl, Bernhard Korte, Jens Vygen 2005-06-07