Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9245075 | Concurrent optimization of timing, area, and leakage power | Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee | 2016-01-26 |
| 8924901 | Look-up based fast logic synthesis | Sanjay Dhar, Vishal Khandelwal, Kok Kiong Lee | 2014-12-30 |
| 7984405 | Method and apparatus for determining the timing of an integrated circuit design | Pei-Hsin Ho | 2011-07-19 |
| 7469392 | Abstraction refinement using controllability and cooperativeness analysis | Pei-Hsin Ho | 2008-12-23 |