Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8711012 | Encoding method, decoding method, encoding device, decoding device, program, and recording medium | Shigeaki Sasaki, Yusuke Hiwasaki, Shoichi Koyama, Kimitaka Tsutsumi | 2014-04-29 |
| 8529220 | High-pressure pump | Yoshihito Suzuki, Shinobu Oikawa | 2013-09-10 |
| 8365978 | Tongue-lid package | Kazuhiro Yoshimura, Hiroko Murai, Hidehisa Tokita, Akihiro Saito | 2013-02-05 |
| 8257067 | High pressure pump | Yoshihito Suzuki, Katsunori Furuta, Tatsumi Oguri, Hiroshi Inoue | 2012-09-04 |
| 8167124 | Slide-action hinge-lid package | Hiroyuki Uesugi, Kazuhiro Yoshimura, Hidehisa Tokita, Akihiro Saito | 2012-05-01 |
| 7131082 | Delay distribution calculation method, circuit evaluation method and false path extraction method | Shuji Tsukiyama, Masakazu Tanaka | 2006-10-31 |
| D527921 | Chair | Yoko Iida | 2006-09-12 |
| 7030688 | Low-pass filter for a PLL, phase-locked loop and semiconductor integrated circuit | Shiro Dosho, Naoshi Yanagisawa, Masaomi Toyama, Keijiro Umehara, Takefumi Yoshikawa +3 more | 2006-04-18 |
| 6769098 | Method of physical design for integrated circuit | Masakazu Tanaka, Shuji Tsukiyama | 2004-07-27 |
| 6727120 | Wiring method in layout design of semiconductor integrated circuit, semiconductor integrated circuit and functional macro | Naoki Hayashi | 2004-04-27 |
| 6684375 | Delay distribution calculation method, circuit evaluation method and false path extraction method | Shuji Tsukiyama, Masakazu Tanaka | 2004-01-27 |
| 6609237 | Routing path finding method for automated routing/designing process and computer-readable storage medium having stored thereon routing path finding program | Koji Hamawaki | 2003-08-19 |
| 6553544 | Method for design of partial circuit | Masakazu Tanaka | 2003-04-22 |
| 6516458 | Layout structure for integrated circuit, method and system for generating layout for CMOS circuit | — | 2003-02-04 |
| 6478688 | Device and method for golf club face alignment | — | 2002-11-12 |
| 6415417 | Method and apparatus for transistor optimization, method and apparatus for layout design of integrated circuit, and integrated circuit | Masakazu Tanaka | 2002-07-02 |
| 6393601 | Layout designing apparatus for integrated circuit, transistor size determining apparatus, circuit characteristic evaluating method, and transistor size determining method | Masakazu Tanaka | 2002-05-21 |
| 6336207 | Method and apparatus for designing LSI layout, cell library for designing LSI layout and semiconductor integrated circuit | Noriko Shinomiya | 2002-01-01 |
| 6330707 | Automatic routing method | Noriko Shinomiya | 2001-12-11 |
| 6292926 | Functional module model, pipelined circuit synthesis and pipelined circuit device | Masakazu Tanaka, Toshiro Akino, Masaharu Imai, Yoshinori Takeuchi | 2001-09-18 |
| 6253351 | Circuit optimization system | Masakazu Tanaka | 2001-06-26 |
| 6209119 | Apparatus and method for synthesizing module | — | 2001-03-27 |
| 6202195 | Semiconductor integrated circuit layout method | Masakazu Tanaka, Noriko Shinomiya | 2001-03-13 |
| 5943486 | Compaction method, compaction apparatus, routing method and routing apparatus | Noriko Shinomiya | 1999-08-24 |
| 5852562 | Method and apparatus for designing an LSI layout utilizing cells having a predetermined wiring height in order to reduce wiring zones | Noriko Shinomiya, Masahiko Toyonaga, Toshiro Akino | 1998-12-22 |