Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9286976 | Apparatuses and methods for detecting write completion for resistive memory | Blake C. Lin, Ananda Roy, Liqiong Wei, Fatih Hamzaoglu | 2016-03-15 |
| 9263121 | Low power transient voltage collapse apparatus and method for a memory cell | Eric A. Karl, Yong-Gee Ng | 2016-02-16 |
| 9230636 | Apparatus for dual purpose charge pump | Pascal A. Meinerzhagen, Jaydeep P. Kulkarni, Muhammad M. Khellah, Dinesh Somasekhar, James W. Tschanz +1 more | 2016-01-05 |
| 9202543 | System and methods using a multiplexed reference for sense amplifiers | El Mehdi Boujamaa | 2015-12-01 |
| 8605479 | Nonvolatile memory architecture | Alexandre Ney, Karl Hofmann | 2013-12-10 |
| 8335121 | Method for implementing an SRAM memory information storage device | Francois Jacquet, Sébastien Barasinski | 2012-12-18 |
| 8331166 | Method and system for reading from memory cells in a memory device | Alexandre Ney | 2012-12-11 |
| 8243490 | Memory with intervening transistor | — | 2012-08-14 |
| 7795917 | High-speed buffer circuit, system and method | Sébastien Barasinski | 2010-09-14 |
| 7782093 | Integrated circuit and method of detecting a signal edge transition | — | 2010-08-24 |
| 7751229 | SRAM memory device with improved write operation and method thereof | Francois Jacquet, Sébastien Barasinski | 2010-07-06 |
| 7630264 | Memory device and testing with write completion detection | Stephany Bouniol, Magali Hage Hassan, Luc Palau | 2009-12-08 |
| 7545686 | Device for setting up a write current in an MRAM type memory and memory comprising | Jean Lasseuguette, Sébastien Barasinski | 2009-06-09 |
| 7489559 | Recursive device for switching over a high potential greater than a nominal potential of a technology in which the device is made and related system and method | Stéphane Gamet | 2009-02-10 |
| 7391661 | Column redundancy system for an integrated circuit memory | — | 2008-06-24 |
| 7372728 | Magnetic random access memory array having bit/word lines for shared write select and read operations | Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel | 2008-05-13 |
| 7333362 | Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane | Philippe Gendrier, Richard Fournel, Sébastien Poirier, Daniel Caspar, Philippe Candelier | 2008-02-19 |
| 7209383 | Magnetic random access memory array having bit/word lines for shared write select and read operations | Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel | 2007-04-24 |
| 7139212 | Memory architecture with segmented writing lines | Sébastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel | 2006-11-21 |
| 7110315 | Switch arrangement for switching a node between different voltages without generating combinational currents | — | 2006-09-19 |
| 6940119 | Non-volatile programmable and electrically erasable memory with a single layer of gate material | Phillipe Gendrier, Richard Fournel | 2005-09-06 |
| 6850112 | Device for controlling a circuit generating reference voltages | — | 2005-02-01 |
| 6728135 | Memory cell of the famos type having several programming logic levels | Daniel Caspar, Richard Fournel | 2004-04-27 |
| 6707697 | FAMOS type non-volatile memory | Richard Fournel | 2004-03-16 |
| 6667909 | Method of erasing a FAMOS memory cell and a corresponding memory cell | Richard Fournel, Daniel Caspar | 2003-12-23 |