Issued Patents All Time
Showing 25 most recent of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12334429 | Co-integrated vertically structured capacitive element and fabrication process | Abderrezak Marzaki, Arnaud Regnier | 2025-06-17 |
| 11817484 | Method for manufacturing an electronic device | Franck Julien, Leo Gave | 2023-11-14 |
| 11626365 | Co-integrated vertically structured capacitive element and fabrication process | Abderrezak Marzaki, Arnaud Regnier | 2023-04-11 |
| 11522057 | Method for manufacturing an electronic device | Franck Julien, Leo Gave | 2022-12-06 |
| 11405223 | Device of physically unclonable function with transistors, and manufacturing method | Francesco La Rosa, Marc Mantelli, Arnaud Regnier | 2022-08-02 |
| 11139303 | Integrated circuit with vertically structured capacitive element, and its fabricating process | Abderrezak Marzaki, Arnaud Regnier, Quentin Hubert, Thomas CABOUT | 2021-10-05 |
| 11081488 | Integrated circuit with vertically structured capacitive element, and its fabricating process | Abderrezak Marzaki, Arnaud Regnier, Quentin Hubert, Thomas CABOUT | 2021-08-03 |
| 11004785 | Co-integrated vertically structured capacitive element and fabrication process | Abderrezak Marzaki, Arnaud Regnier | 2021-05-11 |
| 10971633 | Structure and method of forming a semiconductor device | Francesco La Rosa, Arnaud Regnier | 2021-04-06 |
| 10943862 | Integrated filler capacitor cell device and corresponding manufacturing method | Abderrezak Marzaki, Arnaud Regnier | 2021-03-09 |
| 10818669 | Integrated circuit with vertically structured capacitive element, and its fabricating process | Abderrezak Marzaki, Arnaud Regnier, Quentin Hubert, Thomas CABOUT | 2020-10-27 |
| 10796763 | Method for programming a split-gate memory cell and corresponding memory device | Francesco La Rosa, Marc Mantelli, Arnaud Regnier | 2020-10-06 |
| 10790293 | Compact non-volatile memory device of the type with charge trapping in a dielectric interface | Francesco La Rosa, Arnaud Regnier | 2020-09-29 |
| 10770357 | Integrated circuit with improved resistive region | Benoit Froment, Arnaud Regnier, Abderrezak Marzaki | 2020-09-08 |
| 10686046 | Memory cell comprising non-self-aligned horizontal and vertical control gates | Francesco La Rosa, Arnaud Regnier, Julien Delalleau | 2020-06-16 |
| 10541270 | Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device | Francesco La Rosa, Arnaud Regnier | 2020-01-21 |
| 10438960 | Compact non-volatile memory device of the type with charge trapping in a dielectric interface | Francesco La Rosa, Arnaud Regnier | 2019-10-08 |
| 10403730 | Memory cell comprising non-self-aligned horizontal and vertical control gates | Francesco La Rosa, Arnaud Regnier, Julien Delalleau | 2019-09-03 |
| 10354926 | Integrated circuit with improved resistive region | Benoit Froment, Arnaud Regnier, Abderrezak Marzaki | 2019-07-16 |
| 10332808 | Device comprising multiple gate structures and method of simultaneously manufacturing different transistors | Franck Julien, Emmanuel Richard, Olivier Weber | 2019-06-25 |
| 10192999 | Vertical memory cell with non-self-aligned floating drain-source implant | Marc Mantelli, Arnaud Regnier, Francesco La Rosa, Julien Delalleau | 2019-01-29 |
| 10147733 | Method for forming a PN junction and associated semiconductor device | Francesco La Rosa, Arnaud Regnier | 2018-12-04 |
| 10002906 | Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device | Francesco La Rosa, Arnaud Regnier | 2018-06-19 |
| 9941012 | Twin memory cell interconnection structure | Francesco La Rosa, Arnaud Regnier | 2018-04-10 |
| 9941369 | Memory cell comprising non-self-aligned horizontal and vertical control gates | Francesco La Rosa, Julien Delalleau, Arnaud Regnier | 2018-04-10 |