Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12198973 | Integrated circuit comprising trenches formed in a substrate | Abderrezak Marzaki | 2025-01-14 |
| 12125899 | MOS transistor having substantially parallelepiped-shaped insulating spacers | Arnaud Regnier, Dann MORILLON, Marjorie HESSE | 2024-10-22 |
| 11817484 | Method for manufacturing an electronic device | Stephan Niel, Leo Gave | 2023-11-14 |
| 11640921 | Process for fabricating an integrated circuit comprising a phase of forming trenches in a substrate and corresponding integrated circuit | Abderrezak Marzaki | 2023-05-02 |
| 11522057 | Method for manufacturing an electronic device | Stephan Niel, Leo Gave | 2022-12-06 |
| 11424342 | Fabrication process comprising an operation of defining an effective channel length for MOSFET transistors | Julien Delalleau | 2022-08-23 |
| 11183505 | Process for fabricating medium-voltage transistors and corresponding integrated circuit | Abderrezak Marzaki | 2021-11-23 |
| 11121042 | Production of semiconductor regions in an electronic chip | Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret | 2021-09-14 |
| 10930757 | Method of manufacturing MOS transistor spacers | Arnaud Regnier, Dann MORILLON, Marjorie HESSE | 2021-02-23 |
| 10777552 | Method of simultaneous fabrication of SOI transistors and of transistors on bulk substrate | — | 2020-09-15 |
| 10672644 | Production of semiconductor regions in an electronic chip | — | 2020-06-02 |
| 10553499 | Production of semiconductor regions in an electronic chip | Frédéric Chairat, Noémie Blanc, Emmanuel Blot, Philippe Roux, Gerald Theret | 2020-02-04 |
| 10332808 | Device comprising multiple gate structures and method of simultaneously manufacturing different transistors | Stephan Niel, Emmanuel Richard, Olivier Weber | 2019-06-25 |