Issued Patents All Time
Showing 26–50 of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10615809 | Calibration of a voltage controlled oscillator to trim the gain thereof, using a phase locked loop and a frequency locked loop | Ankit Gupta, Anand Kumar | 2020-04-07 |
| 10566980 | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop | Jeet Narayan Tiwari | 2020-02-18 |
| 10544109 | Process for the preparation of xylene linked cyclam compounds | Hemant Kumar Singh, Sandeep Kumar, Ghanashyam Madhukar Sonavane, Vishal Handa, Chandan Gupta +4 more | 2020-01-28 |
| 10528076 | Clock retiming circuit | Bhavin Odedara | 2020-01-07 |
| 10505552 | Locked loop circuit with reference signal provided by un-trimmed oscillator | Anand Kumar, Nitin Jain | 2019-12-10 |
| 10254783 | External clock based clock generator | Bhavin Odedara, Raghu Voleti, Srikanth Bojja | 2019-04-09 |
| 10228746 | Dynamic distributed power control circuits | Voleti Siva Raghu Ram, Bhavin Odedara, Sitaram Banda | 2019-03-12 |
| 10224928 | On-die impedance calibration | Shiv Harit Mathur, Ramakrishnan Subramanian | 2019-03-05 |
| 10198014 | Low leakage low dropout regulator with high bandwidth and power supply rejection | Kapil Kumar Tyagi | 2019-02-05 |
| 10177773 | Programmable clock divider | Jeet Narayan Tiwari | 2019-01-08 |
| 10033518 | Data on clock lane of source synchronous links | Tapas Nandy | 2018-07-24 |
| 10027333 | Phase locked loops having decoupled integral and proportional paths | Abhirup Lahiri, Gagan Midha | 2018-07-17 |
| 9794054 | Data on clock lane of source synchronous links | Tapas Nandy | 2017-10-17 |
| 9746871 | Noise canceling current mirror circuit for improved PSR | Abhirup Lahiri | 2017-08-29 |
| 9647699 | Dual supply voltage power harvesting in an open drain transmitter circuit | Tapas Nandy | 2017-05-09 |
| 9564904 | Asynchronous high-speed programmable divider | Jeet Narayan Tiwari | 2017-02-07 |
| 9559902 | Distributed state model for system configuration synchronization | Bruce G. Payette, Narayanan Lakshmanan, Xuejian Pan, Sharath Gopalappa | 2017-01-31 |
| 9440979 | Process for the preparation of pralatrexate | Saswata Lahiri, Hemant Kumar Singh, Nilendu Panda, Vishal Handa, Azim Abul +3 more | 2016-09-13 |
| 9367619 | Large scale real-time multistaged analytic system using data contracts | Atul Katiyar, Purushottam Amradkar | 2016-06-14 |
| 9331671 | Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods | Paramjeet Singh Sahni, Tapas Nandy, Manish Garg | 2016-05-03 |
| 9325324 | Phase locked loop (PLL) circuit with compensated bandwidth across process, voltage and temperature | Anand Kumar, Abhirup Lahiri | 2016-04-26 |
| 9294106 | Capacitance multiplier and loop filter noise reduction in a PLL | Abhirup Lahiri | 2016-03-22 |
| 9146574 | Noise canceling current mirror circuit for improved PSR | Abhirup Lahiri | 2015-09-29 |
| 9148099 | HDMI receiver | Tapas Nandy | 2015-09-29 |
| 9000193 | Process for the preparation of cabazitaxel | Saswata Lahiri, Abul Azim, Nilendu Panda, Bhuwan Bhaskar Mishra, Sunil Sanghani | 2015-04-07 |