Issued Patents All Time
Showing 25 most recent of 64 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431909 | SSD with reference clock loss tolerant oscillator | Pikul Sarkar, Bhavin Odedara | 2025-09-30 |
| 11984168 | High speed toggle mode transmitter with capacitive boosting | Shiv Harit Mathur, Ramakrishnan Subramanian, Dmitry Vaysman | 2024-05-14 |
| 11581305 | High voltage protection for high-speed data interface | Ramakrishnan Subramanian, Sitaram Banda | 2023-02-14 |
| 11539207 | Snapback electrostatic discharge protection for electronic circuits | Shiv Harit Mathur | 2022-12-27 |
| 11532208 | Gaming machine with concurrent activatable wager options and individually selectable wager amounts | Billy Tam, Gaurav Goel, Pradip Rangari | 2022-12-20 |
| 11474546 | Method of operating a low dropout regulator by selectively removing and replacing a DC bias from a power transistor within the low dropout regulator | Kapil Kumar Tyagi | 2022-10-18 |
| 11465999 | Process for preparing Alectinib or a pharmaceutically acceptable salt thereof | Vinod Singh Tomar, Abul Azim, Saswata Lahiri, Walter Cabri | 2022-10-11 |
| 11210241 | High-level output voltage training for non-volatile memory | Ashish Savadia, Jayanth Mysore Thimmaiah, Ramakrishnan Subramanian, Rampraveen Somasundaram, Shiv Harit Mathur +4 more | 2021-12-28 |
| 11171619 | Transconductance boosted cascode compensation for amplifier | Prashutosh GUPTA | 2021-11-09 |
| 11098037 | Process for preparing alectinib or a pharmaceutically acceptable salt thereof | Vinod Singh Tomar, Abul Azim, Saswata Lahiri, Walter Cabri | 2021-08-24 |
| 11095297 | Phase locked loop (PLL) circuit with voltage controlled oscillator (VCO) having reduced gain | Sagnik Mukherjee | 2021-08-17 |
| 11079824 | Current distribution from different power sources | Bhavin Odedara, Raghu Voleti | 2021-08-03 |
| 11062565 | Gaming machine with concurrent activatable wager options and individually selectable wager amounts | Billy Tam, Gaurav Goel, Pradip Rangari | 2021-07-13 |
| 11056880 | Snapback electrostatic discharge protection for electronic circuits | Shiv Harit Mathur | 2021-07-06 |
| 11043488 | High voltage protection for high-speed data interface | Ramakrishnan Subramanian, Sitaram Banda | 2021-06-22 |
| 11016519 | Process compensated gain boosting voltage regulator | Ankit Gupta, Prashutosh GUPTA | 2021-05-25 |
| 10911053 | Phase locked loop design with reduced VCO gain | Kapil Kumar Tyagi | 2021-02-02 |
| 10878860 | Multi-level signaling scheme for memory interface | Shiv Harit Mathur, Ramakrishnan Subramanian | 2020-12-29 |
| 10861508 | Transmitting DBI over strobe in nonvolatile memory | Shiv Harit Mathur, Ramakrishnan Subramanian | 2020-12-08 |
| 10862487 | Locked loop circuit with reference signal provided by un-trimmed oscillator | Anand Kumar, Nitin Jain | 2020-12-08 |
| 10838901 | System and method for a reconfigurable controller bridge chip | Vijay Chinchole, Siva Raghu Ram Voleti, Ramakrishnan Subramanian, Shiv Harit Mathur, Yan Li +1 more | 2020-11-17 |
| 10840915 | Use of a raw oscillator and frequency locked loop to quicken lock time of frequency locked loop | Jeet Narayan Tiwari | 2020-11-17 |
| 10795389 | Low leakage low dropout regulator with high bandwidth and power supply rejection, and associated methods | Kapil Kumar Tyagi | 2020-10-06 |
| 10771073 | Frequency synthesizer with dynamically selected level shifting of the oscillating output signal | — | 2020-09-08 |
| 10635843 | Simulation modeling frameworks for controller designs | Amit Garg, Ashutosh Pandey | 2020-04-28 |