Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12019406 | Using time-to-digital converters to delay signals with high accuracy and large range | James D. Barnette | 2024-06-25 |
| 11888493 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Douglas F. Pastorello, Raghunandan Kolar Ranganathan | 2024-01-30 |
| 11563441 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Douglas F. Pastorello, Raghunandan Kolar Ranganathan | 2023-01-24 |
| 11526135 | Using time-to-digital converters to delay signals with high accuracy and large range | James D. Barnette | 2022-12-13 |
| 11283459 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Douglas F. Pastorello, Raghunandan K. Ranganathan | 2022-03-22 |
| 10727844 | Reference clock frequency change handling in a phase-locked loop | Xue-Mei Gong, James D. Barnette | 2020-07-28 |
| 10727845 | Use of a virtual clock in a PLL to maintain a closed loop system | James D. Barnette | 2020-07-28 |
| 10651862 | Locking a PLL to the nearest edge of the input clock when the input clock is divided down before use in the PLL | James D. Barnette | 2020-05-12 |