Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11888493 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Krishnan Balakrishnan, Raghunandan Kolar Ranganathan | 2024-01-30 |
| 11563441 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Krishnan Balakrishnan, Raghunandan Kolar Ranganathan | 2023-01-24 |
| 11283459 | Calibration of a time-to-digital converter using a virtual phase-locked loop | Timothy A. Monk, Krishnan Balakrishnan, Raghunandan K. Ranganathan | 2022-03-22 |
| 10833682 | Calibration of an interpolative divider using a virtual phase-locked loop | Timothy A. Monk | 2020-11-10 |
| 10819353 | Spur cancellation in a PLL system with an automatically updated target spur frequency | Timothy A. Monk | 2020-10-27 |
| 10511312 | Metastable-free output synchronization for multiple-chip systems and the like | Timothy A. Monk, Ping Lu, Michael Lu | 2019-12-17 |
| 9588497 | Differential voltage-controlled oscillator analog-to-digital converter using input-referred offset | Timothy A. Monk, Rajesh Thirugnanam | 2017-03-07 |
| 8041975 | Programmable I/O cell capable of holding its state in power-down mode | Biranchinath Sahu, Golam R. Chowdhury | 2011-10-18 |
| 8020010 | Memory power controller | Patrick De Bakker, Louis Nervegna | 2011-09-13 |
| 8010819 | Microcontroller unit (MCU) with power saving mode | Douglas R. Holberg, William Durbin, Biranchinath Sahu, Golam R. Chowdhury | 2011-08-30 |
| 7562275 | Tri-level test mode terminal in limited terminal environment | Richard J. Juhn | 2009-07-14 |
| 7551009 | High-speed divider with reduced power consumption | Akhil Garlapati, Lizhong Sun | 2009-06-23 |
| 7502434 | Frequency detector including a variable delay filter | Eric T. King | 2009-03-10 |
| 7441131 | MCU with power saving mode | Douglas R. Holberg, William Durbin, Biranchinath Sahu, Golam R. Chowdhury | 2008-10-21 |
| 7405601 | High-speed divider with pulse-width control | Akhil Garlapati, Lizhong Sun, Richard J. Juhn, Axel Thomsen | 2008-07-29 |
| 7373533 | Programmable I/O cell capable of holding its state in power-down mode | Biranchinath Sahu, Golam R. Chowdhury | 2008-05-13 |
| 7187216 | Phase selectable divider circuit | Lizhong Sun, Richard J. Juhn, Axel Thomsen | 2007-03-06 |
| 7113009 | Programmable frequency divider | Lizhong Sun, Bruce P. Del Signore, Axel Thomsen | 2006-09-26 |
| 6831523 | Auto-detection between referenceless and reference clock mode of operation | Michael H. Perrott | 2004-12-14 |
| 6760854 | Method and apparatus for handling a framing error at a serial interface by forcing invalid commands to be read upon determine the command is invalid | — | 2004-07-06 |
| 6657488 | Offset correction and slicing level adjustment for amplifier circuits | Eric T. King, Michael H. Perrott | 2003-12-02 |
| 6557051 | Throughput for a serial interface | — | 2003-04-29 |
| 6531906 | Delay systems and methods using a variable delay SINC filter | William F. Gardei | 2003-03-11 |
| 6522982 | Energy-to-pulse converter systems, devices, and methods wherein the output frequency is greater than the calculation frequency and having output phasing | Eric T. King | 2003-02-18 |
| 6487674 | Single wire interface for an analog to digital converter | Joe White, Jerome E. Johnston | 2002-11-26 |