Issued Patents All Time
Showing 26–50 of 57 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7547601 | Low power electrically alterable nonvolatile memory cells and arrays | — | 2009-06-16 |
| 7411244 | Low power electrically alterable nonvolatile memory cells and arrays | — | 2008-08-12 |
| 7375398 | High voltage FET gate structure | Bin Wang | 2008-05-20 |
| 7372734 | Methods of operating electrically alterable non-volatile memory cell | — | 2008-05-13 |
| 7297634 | Method and apparatus for semiconductor device and semiconductor memory device | — | 2007-11-20 |
| 7257033 | Inverter non-volatile memory cell and array system | Bin Wang, William T. Colleran | 2007-08-14 |
| 7180125 | P-channel electrically alterable non-volatile memory cell | — | 2007-02-20 |
| 7144778 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Sohrab Kianian | 2006-12-05 |
| 7115942 | Method and apparatus for nonvolatile memory | — | 2006-10-03 |
| 7107941 | Safety device of collar for pet | — | 2006-09-19 |
| 7098499 | Electrically alterable non-volatile memory cell | — | 2006-08-29 |
| 7074672 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor | Sohrab Kianian | 2006-07-11 |
| 7018897 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate spacers | — | 2006-03-28 |
| 7015102 | Method of forming floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells made thereby | — | 2006-03-21 |
| 6958513 | Floating-gate memory cell having trench structure with ballistic-charge injector, and the array of memory cells | — | 2005-10-25 |
| 6952033 | Semiconductor memory array of floating gate memory cells with buried bit-line and raised source line | Sohrab Kianian | 2005-10-04 |
| 6917069 | Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor | Sohrab Kianian | 2005-07-12 |
| 6882572 | Method of operating a semiconductor memory array of floating gate memory cells with horizontally oriented edges | Bing Yeh | 2005-04-19 |
| 6868015 | Semiconductor memory array of floating gate memory cells with control gate spacer portions | — | 2005-03-15 |
| 6861698 | Array of floating gate memory cells having strap regions and a peripheral logic device region | — | 2005-03-01 |
| 6855980 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Amitay Levi | 2005-02-15 |
| 6773974 | Method of forming a semiconductor array of floating gate memory cells and strap regions | Amitay Levi | 2004-08-10 |
| 6773989 | Self aligned method of forming a semiconductor memory array of floating gate memory cells with control gate protruding portions | — | 2004-08-10 |
| 6756633 | Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges | Bing Yeh | 2004-06-29 |
| 6743674 | Method of forming a semiconductor array of floating gate memory cells and strap regions, and a memory array and strap regions made thereby | — | 2004-06-01 |