Daniel E. Lenoski — 33 Patents at Silicon Graphics

Daniel E. Lenoski has been granted 33 US patents while listed as an inventor at Silicon Graphics. The first was granted in 1988 and the most recent in February 2012. Daniel E. Lenoski ranks #105,480 of 4,157,543 US inventors in our database (top 2.5%). Patent records list Daniel E. Lenoski in Mountain View, CA, US.

Issued Patents All Time

Showing 1–25 of 33 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8117369	Input-output module for operation in memory module socket and method for extending a memory interface for input-output operations	Satyanarayana Nishtala, Thomas L. Lyon	2012-02-14	$25,137,000
7886103	Input-output module, processing platform and method for extending a memory interface for input-output operations	Satyanarayana Nishtala, Thomas L. Lyon	2011-02-08	$17,690,000
7500068	Method and system for managing memory in a multiprocessor system	Jeffrey S. Kuskin, William A. Huffman, Michael S. Woodacre	2009-03-03	$284,000
7069306	Providing shared and non-shared access to memory in a system with plural processor coherence domains	Jeffrey S. Kuskin, William A. Huffman, Michael S. Woodacre	2006-06-27
6990063	Distributing fault indications and maintaining and using a data structure indicating faults to route traffic in a packet switching system	William N. Eatherton, John Andrew Fingerhut, Jonathan S. Turner	2006-01-24	$49,969,000
6981101	Method and system for maintaining data at input/output (I/O) interfaces for a multiprocessor system	Steven C. Miller, Kevin M. Knecht, George M. Hopkins, Michael S. Woodacre	2005-12-27
6826186	Method and apparatus for distributing packets across multiple paths leading to a destination	Zubin Dittia, John Andrew Fingerhut	2004-11-30	$116,123,000
6816492	Resequencing packets at output ports without errors using packet timestamps and timestamp floors	Jonathan S. Turner	2004-11-09	$102,099,000
6747972	Method and apparatus for reducing the required size of sequence numbers used in resequencing packets	William N. Eatherton, Zubin Dittia, John Andrew Fingerhut	2004-06-08	$141,017,000
6735173	Method and apparatus for accumulating and distributing data items within a packet switching system	Jonathan S. Turner	2004-05-11	$74,444,000
6182195	System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer	James Laudon	2001-01-30	$2,433,000
6141741	Computer system with a shared address bus and pipelined write operations	Curtis Priem, Satyanarayana Nishtala, Michael G. Lavelle, Thomas P. Webber, Peter A. Mehring +2 more	2000-10-31	$145,731,000
6049476	High memory capacity DIMM with data and state memory	James Laudon, John C. Manton, Michael E. Anderson	2000-04-11	$14,877,000
5991895	System and method for multiprocessor partitioning to support high availability	James Laudon	1999-11-23	$12,836,000
5974456	System and method for input/output flow control in a multiprocessor computer system	Kianoosh Naghshineh	1999-10-26	$6,134,000
5822381	Distributed global clock system	David Parry, Charles E. Narad	1998-10-13	$9,478,000
5790447	High-memory capacity DIMM with data and state memory	James Laudon, John C. Manton	1998-08-04	$5,945,000
5787476	System and method for maintaining coherency of virtual-to-physical memory translations in a multiprocessor computer	James Laudon	1998-07-28	$31,411,000
5768529	System and method for the synchronous transmission of data in a communication network utilizing a source clock signal to latch serial data into first registers and a handshake signal to latch parallel data into second registers	Ronald E. Nikel, Michael B. Galles	1998-06-16	$8,414,000
5727150	Apparatus and method for page migration in a non-uniform memory access (NUMA) system	James Laudon	1998-03-10	$21,631,000
5686730	Dimm pair with data memory and state memory	James Laudon, John C. Manton	1997-11-11	$39,604,000
5669008	Hierarchical fat hypercube architecture for parallel processing systems	Michael B. Galles	1997-09-16	$69,377,000
5634110	Cache coherency using flexible directory bit vectors	James Laudon	1997-05-27	$44,812,000
5309561	Synchronous processor unit with interconnected, separately clocked processor sections which are automatically synchronized for data transfer operations	Leonard E. Overhouse	1994-05-03	$15,101,000
5185870	System to determine if modification of first macroinstruction to execute in fewer clock cycles	—	1993-02-09	$17,173,000

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Daniel E. Lenoski — 33 Patents

Issued Patents All Time

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