Issued Patents All Time
Showing 76–86 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5671371 | Bus control system | Nobukazu Kondo, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida, Takehisa Hayashi | 1997-09-23 |
| 5657458 | Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment | Nobukazu Kondo, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa | 1997-08-12 |
| 5604874 | Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment | Nobukazu Kondo, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa | 1997-02-18 |
| 5590290 | Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement | Nobukazu Kondo, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa | 1996-12-31 |
| 5532508 | Semiconductor device with LDD structure | Tomoya Baba | 1996-07-02 |
| 5428753 | Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment | Nobukazu Kondo, Hideaki Gemma, Tetsuhiko Okada, Kazuhiko Komori, Koichi Okazawa | 1995-06-27 |
| 5426063 | Method of making a field effect transistor with submicron channel length and threshold implant using oblique implantation | Tomoya Baba | 1995-06-20 |
| 5377341 | Buffer storage control system | Toshiyuki Kinoshita, Akio Yamamoto, Yasuhisa Tamura | 1994-12-27 |
| 5349656 | Task scheduling method in a multiprocessor system where task selection is determined by processor identification and evaluation information | Toshiyuki Kinoshita, Akio Yamamoto, Yasuhisa Tamura | 1994-09-20 |
| 5333289 | Main memory addressing system | Masaya Watanabe, Toshiyuki Kinoshita, Yasuhisa Tamura, Masaichiro Yoshioka | 1994-07-26 |
| 5317704 | Storage relocating method and hierarchy storage system utilizing a cache memory | Satoshi Izawa, Masaya Watanabe | 1994-05-31 |