Issued Patents All Time
Showing 51–75 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6249463 | Address latch enable signal control circuit for electronic memories | — | 2001-06-19 |
| 6212128 | Address transition detector in semiconductor memories | — | 2001-04-03 |
| 6212096 | Data reading path management architecture for a memory device, particularly for non-volatile memories | — | 2001-04-03 |
| 6195286 | Circuit and method for reading a non-volatile memory | — | 2001-02-27 |
| 6175521 | Voltage regulator for programming electrically programmable non-volatile memory cells in a cell matrix | Marco Fontana | 2001-01-16 |
| 6148413 | Memory under test programming and reading device | Marco Fontana | 2000-11-14 |
| 6100740 | Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit | — | 2000-08-08 |
| 6081911 | Method and circuit architecture for testing a non-volatile memory device | — | 2000-06-27 |
| 6078523 | Gain modulated sense amplifier and method of operating the same | — | 2000-06-20 |
| 6061273 | Pre-charge step determining circuit of a generic bit line, particularly for non-volatile memories | — | 2000-05-09 |
| 6046619 | Asymmetrical pulsive delay network | — | 2000-04-04 |
| RE36579 | Sense circuit for reading data stored in nonvolatile memory cells | Marco Olivo | 2000-02-22 |
| 5986954 | Self-regulated equalizer, particularly for sense amplifiers | — | 1999-11-16 |
| 5968183 | Semiconductor memory device with clocked column redundancy and time-shared redundancy data transfer approach | — | 1999-10-19 |
| 5959476 | Circuit and method for generating a power-on reset signal | — | 1999-09-28 |
| 5959917 | Circuit for detecting the coincidence between a binary information unit stored therein and an external datum | — | 1999-09-28 |
| 5959935 | Synchronization signal generation circuit and method | — | 1999-09-28 |
| 5946237 | Nonvolatile memory device capable of reading data with a reduced number of word lines | — | 1999-08-31 |
| 5936907 | Method for detecting redunded defective addresses in a memory device with redundancy | — | 1999-08-10 |
| 5917768 | Memory architecture for flexible reading management, particularly for non-volatile memories, having noise-immunity features, matching device performance, and having optimized throughout | — | 1999-06-29 |
| 5914901 | Integrated circuit for generating initialization signals for memory cell sensing circuits | — | 1999-06-22 |
| 5914867 | Voltage generator-booster for supplying a pulsating voltage having approximately constant voltage levels | — | 1999-06-22 |
| 5905678 | Control circuit of an output buffer | — | 1999-05-18 |
| 5903166 | Circuit for immunizing an integrated circuit from noise affecting enable signals of the integrated circuit | — | 1999-05-11 |
| 5901087 | Gain modulated sense amplifier | — | 1999-05-04 |