Issued Patents All Time
Showing 26–50 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6882001 | Electrically-programmable non-volatile memory cell | — | 2005-04-19 |
| 6826083 | Method for reducing spurious erasing during programming of a nonvolatile NROM | — | 2004-11-30 |
| 6804756 | Synchronization circuit for read paths of an electronic memory | — | 2004-10-12 |
| 6701419 | Interlaced memory device with random or sequential access | Francesco Tomaiuolo, Salvatore Nicosia | 2004-03-02 |
| 6700819 | Memory with improved differential reading system | — | 2004-03-02 |
| 6696990 | Binary encoding circuit | — | 2004-02-24 |
| 6594180 | Semiconductor memory system | — | 2003-07-15 |
| 6587913 | Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode | Fabrizio Campanale, Salvatore Nicosia, Francesco Tomaiuolo, Luca De Ambroggi, Promod Kumar | 2003-07-01 |
| 6580637 | Semiconductor memory architecture | — | 2003-06-17 |
| 6552952 | Column multiplexer for semiconductor memories | — | 2003-04-22 |
| 6549485 | Control and timing structure for a memory | — | 2003-04-15 |
| 6525591 | Circuit for selectively enabling one among a plurality of circuit alternatives of an integrated circuit | — | 2003-02-25 |
| 6501700 | Internal addressing structure of a semiconductor memory | — | 2002-12-31 |
| 6477625 | Method and system for reading a memory by applying control signals thereto | Marco Fontana | 2002-11-05 |
| 6438669 | Timesharing internal bus, particularly for non-volatile memories | Paolo Rolandi, Marco Fontana, Antonio Barcella | 2002-08-20 |
| 6438040 | Enabling circuit for output devices in electronic memories | — | 2002-08-20 |
| 6424575 | Synchronous output buffer, particularly for non-volatile memories | — | 2002-07-23 |
| 6373781 | Priority determining circuit for non-volatile memory | — | 2002-04-16 |
| 6362658 | Decoder for memories having optimized configuration | — | 2002-03-26 |
| 6356505 | Internal regeneration of the address latch enable (ALE) signal of a protocol of management of a burst interleaved memory and related circuit | Salvatore Nicosia, Fabrizio Campanale, Francesco Tomaiuolo, Luca De Ambroggi | 2002-03-12 |
| 6351434 | Synchronous counter for electronic memories | — | 2002-02-26 |
| 6330188 | Data read circuit for non volatile memory cells | — | 2001-12-11 |
| 6324238 | Bit counter stage, particularly for memories | — | 2001-11-27 |
| 6320440 | Method for selectively enabling alternative circuits | — | 2001-11-20 |
| 6275416 | Pulse generator circuit, particularly for non-volatile memories | — | 2001-08-14 |