Issued Patents All Time
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11754624 | Programmable scan chain debug technique | Bharat P. Londhe, Deep Neema | 2023-09-12 |
| 10685730 | Circuit including efficient clocking for testing memory interface | Jay Shah, Sachin Shivanand Bastimane | 2020-06-16 |
| 10459029 | On-chip clock control monitoring | Paras Gangwal, Surbhi Bansal, Sachin Shivanand Bastimane | 2019-10-29 |
| 8898527 | At-speed scan testing of clock divider logic in a clock module of an integrated circuit | Priyesh Kumar, Ramesh C. Tekumalla | 2014-11-25 |
| 8738978 | Efficient wrapper cell design for scan testing of integrated | Ramesh C. Tekumalla, Partho Tapan Chaudhuri, Priyesh Kumar | 2014-05-27 |