Issued Patents All Time
Showing 26–45 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9135106 | Read level adjustment using soft information | Anthony Dwayne Weathers, Richard David Barndt | 2015-09-15 |
| 9136011 | Soft information module | Anthony Dwayne Weathers, Richard David Barndt | 2015-09-15 |
| 9110822 | Method and device for write abort protection | Uday Chandrasekhar, Jianmin Huang, Steven T. Sprouse, Nian Niles Yang | 2015-08-18 |
| 9105333 | On-chip copying of data between NAND flash memory and ReRAM of a memory die | Sergey Anatolievich Gorobets, Manuel Antonio D'Abreu | 2015-08-11 |
| 9053790 | Counter for write operations at a data storage device | Manuel Antonio D'Abreu | 2015-06-09 |
| 9047984 | Asymmetric log-likelihood ratio for flash channel | — | 2015-06-02 |
| 9042160 | Memory device with resistive random access memory (ReRAM) | Sergey Anatolievich Gorobets, Aaron K. Olbrich, Manuel Antonio D'Abreu | 2015-05-26 |
| 9021343 | Parity scheme for a data storage device | Manuel Antonio D'Abreu | 2015-04-28 |
| 9015561 | Adaptive redundancy in three dimensional memory | — | 2015-04-21 |
| 8996838 | Structure variation detection for a memory having a three-dimensional memory configuration | Manuel Antonio D'Abreu | 2015-03-31 |
| 8954820 | Reduced complexity non-binary LDPC decoding algorithm | Majid Nemati Anaraki, Richard David Barndt | 2015-02-10 |
| 8942028 | Data reprogramming for a data storage device | — | 2015-01-27 |
| 8848438 | Asymmetric log-likelihood ratio for MLC flash channel | — | 2014-09-30 |
| 8762798 | Dynamic LDPC code rate solution | Richard David Barndt | 2014-06-24 |
| 8656263 | Trellis-coded modulation in a multi-level cell flash memory device | Anthony Dwayne Weathers, Richard David Barndt | 2014-02-18 |
| 8605501 | System and method for determining data dependent noise calculation for a flash channel | Richard David Barndt, Anthony Dwayne Weathers | 2013-12-10 |
| 8566667 | Low density parity check code decoding system and method | Levente Peter Jakab, Dillip K. Dash, Rohit Komatineni | 2013-10-22 |
| 8484519 | Optimal programming levels for LDPC | Anthony Dwayne Weathers, Richard David Barndt | 2013-07-09 |
| 8255768 | Interlaced iterative system design for 1K-byte block with 512-byte LDPC codewords | Sivagnanam Parthasarathy, Shayan Srinivasa Garani, Anthony Dwayne Weathers, Richard David Barndt | 2012-08-28 |
| 8055973 | Channel constrained code aware interleaver | Shayan Srinivasa Garani, Nicholas J. Richardson, Sivagnanam Parthasarathy | 2011-11-08 |