Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11955980 | Electronic apparatus and method for reducing coarse lock time of phase locked loop (PLL) | Venkatasuryam Setty ISSA, Subba Reddy SIDDAMURTHY, Aswani Aditya Kumar Tadinada | 2024-04-09 |
| 11381232 | Duty cycle correction method and circuit thereof | Aswani Aditya Kumar Tadinada, Kishan Reddy Gonapati | 2022-07-05 |