Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11955980 | Electronic apparatus and method for reducing coarse lock time of phase locked loop (PLL) | Venkatasuryam Setty ISSA, Aswani Aditya Kumar Tadinada, Vasu Bevara | 2024-04-09 |
| 11303480 | Method and system for providing an equalizer with a split folded cascode architecture | Venkatasuryam Setty ISSA, Aswani Aditya Kumar Tadinada | 2022-04-12 |