Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Debaditya Mukherjee — 9 Patents

RMRaza Microelectronics: 3 patents #2 of 36Top 6%
UNUnisys: 3 patents #613 of 2,028Top 35%
NMNetlogic Microsystems: 1 patents #111 of 186Top 60%
RMRmi: 1 patents #12 of 42Top 30%
LSLsi: 1 patents #3,174 of 3,238Top 100%
California: #67,547 of 386,348 inventorsTop 20%
Overall (All Time): #535,341 of 4,157,543Top 15%
9 Patents All Time
Debaditya Mukherjee has been granted 9 US patents while listed as an inventor at Raza Microelectronics. The first was granted in 1990 and the most recent in August 2013. Debaditya Mukherjee ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Debaditya Mukherjee in معلمی نژاد, CA, US.

Patents per Year

Patents granted per year, 1990 to 2013Bar chart with a peak of 2 patents in 1990.peak 21990: 2 patents19901991: 1 patents19912007: 2 patents20072008: 2 patents20082012: 1 patents20122013: 1 patents2013

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8503457 Method of forming a digital or analog multiplexing data frame Addepalli Sateesh Kumar, Chandrasekaran Nageswara Gupta, Tushar R. Shah, Thomas Woo, Khalid Sheikh +1 more 2013-08-06
8230263 Automated specification based functional test generation infrastructure Anil Raj Gopalakrishnan 2012-07-24
7333512 Dynamic mixing TDM data with data packets Addepalli Sateesh Kumar, Chandrasekaran Nageswara Gupta, Tushar R. Shah, Thomas Woo, Khalid Seikh +1 more 2008-02-19
7327758 Method of generating, transmitting, receiving and recovering synchronous frames with non-standard speeds Addepalli Sateesh Kumar, Chandrasekaran Nageswara Gupta, Tushar R. Shah, Thomas Woo, Khalid Seikh +1 more 2008-02-05
7173927 Hybrid network to carry synchronous and asynchronous traffic over symmetric and asymmetric links Addepalli Sateesh Kumar, Tushar R. Shah, Chandrasekaran Nageswara Gupta, Thomas Woo, Khalid Seikh +1 more 2007-02-06
7165102 Adaptive link quality management for wireless medium Tushar R. Shah, Chandrasekaran Nageswara Gupta, Addepalli Sateesh Kumar, Thomas Woo, Khalid Seikh +2 more 2007-01-16
5006787 Self-testing circuitry for VLSI units Haluk Katircioglu, John A. De Beule 1991-04-09 $3,708,000
4932028 Error log system for self-testing in very large scale integrated circuit (VLSI) units Haluk Katircioglu, John A. De Beule, Gary C. Whitlock 1990-06-05 $22,703,000
4918378 Method and circuitry for enabling internal test operations in a VLSI chip Haluk Katircioglu, John A. De Beule 1990-04-17 $5,007,000