Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12278600 | Amplifier bias circuit | Valery S. Kaper, Steven M. Lardizabal | 2025-04-15 |
| 12028059 | Common gate input circuit for III/V D-mode buffered FET logic (BFL) | — | 2024-07-02 |
| 11682721 | Asymmetrically angled gate structure and method for making same | Matthew DeJarld, Adam Lyle Moldawer, Kenneth A. Wilson | 2023-06-20 |
| 11476154 | Field effect transistor having improved gate structures | Jeffrey R. LaRoche, Paul J. Duval, Kelly P. Ip | 2022-10-18 |
| 11145735 | Ohmic alloy contact region sealing layer | Paul J. Duval, James W. McClymonds, Paul M. Alcorn, Philip C. Balas, II, Michael S. Davis | 2021-10-12 |
| 10593665 | Field effect transistor (FET) structure with integrated gate connected diodes | Raghuveer Mallavarpu | 2020-03-17 |
| 10447208 | Amplifier having a switchable current bias circuit | Valery S. Kaper, Steven M. Lardizabal | 2019-10-15 |
| 10277176 | Bias circuitry for depletion mode amplifiers | Alan J. Bielunis, Istvan Rodriguez, Zhaoyang Wang | 2019-04-30 |
| 10103137 | Field effect transistor (FET) structure with integrated gate connected diodes | Raghuveer Mallavarpu | 2018-10-16 |
| 9960740 | Bias circuitry for depletion mode amplifiers | Alan J. Bielunis, Istvan Rodriguez, Zhaoyang Wang | 2018-05-01 |
| 9799645 | Field effect transistor (FET) structure with integrated gate connected diodes | Raghuveer Mallavarpu | 2017-10-24 |
| 9793859 | Amplifier output power limiting circuitry | Valery S. Kaper | 2017-10-17 |
| 9634613 | Bias circuit having reduced power consumption | Edward A. Watters, Christopher M. Laighton | 2017-04-25 |
| 9478508 | Microwave integrated circuit (MMIC) damascene electrical interconnect for microwave energy transmission | Jeffrey R. LaRoche, Thomas E. Kazior, Kelly P. Ip | 2016-10-25 |
| 9419083 | Semiconductor structures having a gate field plate and methods for forming such structure | Eduardo M. Chumbes | 2016-08-16 |
| 9356045 | Semiconductor structure having column III-V isolation regions | Jonathan P. Comeau, Jeffrey R. LaRoche | 2016-05-31 |
| 8853745 | Silicon based opto-electric circuits | Kamal Tabatabaie, Jeffrey R. LaRoche, Valery S. Kaper, Kelly P. Ip | 2014-10-07 |
| 8854140 | Current mirror with saturated semiconductor resistor | Frank J. DeCaro, John C. Tremblay | 2014-10-07 |
| 8816184 | Thermoelectric bias voltage generator | — | 2014-08-26 |
| 8344359 | Transistor having thermo electron cooling | Nicholas J. Kolias | 2013-01-01 |
| 8198942 | Integrated thermoelectric protection circuit for depletion mode power amplifiers | — | 2012-06-12 |
| 8154432 | Digital to analog converter (DAC) having high dynamic range | Valery S. Kaper | 2012-04-10 |
| 7994550 | Semiconductor structures having both elemental and compound semiconductor devices on a common substrate | Valery S. Kaper, Jeffrey R. LaRoche, Kamal Tabatabaie | 2011-08-09 |
| 7852136 | Bias network | — | 2010-12-14 |
| 7834456 | Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate | Kamal Tabatabaie, Michael S. Davis, Jeffrey R. LaRoche, Valery S. Kaper | 2010-11-16 |