MI

Marcus Van Ierssel

RA Rambus: 12 patents #135 of 549Top 25%
CS Cadence Design Systems: 4 patents #399 of 2,263Top 20%
MC Movellus Circuits: 2 patents #11 of 16Top 70%
SC Semtech Canada: 1 patents #4 of 26Top 20%
Overall (All Time): #230,937 of 4,157,543Top 6%
19
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12425014 Self-aligning interconnect for a digital system Vikram Karvat, Jeffrey Alan Fredenburg, Brian Che Yuen Lam, David M. Moore, Saif Elam 2025-09-23
12368447 Clock generator system with dynamic frequency crossover Xiao Wu 2025-07-22
12057975 Live offset cancellation of the decision feedback equalization data slicers Mohammad Sadegh Jalali 2024-08-06
11881883 Pattern detection based parameter adaptation Nanyan Wang 2024-01-23
11831323 Methods and circuits for reducing clock jitter Prabhnoor Singh Kainth, Nanyan Wang 2023-11-28
11804846 Phase-locked loop with phase information multiplication George Ng 2023-10-31
11742874 Matched digital-to-analog converters Ravi Shivnaraine 2023-08-29
11671108 Offset calibration for successive approximation register analog to digital converter Kenneth C. Dyer 2023-06-06
11671286 Live offset cancellation of the decision feedback equalization data slicers Mohammad Sadegh Jalali 2023-06-06
11601151 Pattern detection based parameter adaptation Nanyan Wang 2023-03-07
11569975 Baud-rate clock recovery lock point control 2023-01-31
11539374 Matched digital-to-analog converters Ravi Shivnaraine 2022-12-27
11477059 Circuits and methods for detecting and unlocking edge-phase lock Nanyan Wang 2022-10-18
11342929 Offset calibration for successive approximation register analog to digital converter Kenneth C. Dyer 2022-05-24
11206031 Phase rotator non-linearity reduction Dominic DICLEMENTE 2021-12-21
10855297 Phase rotator non-linearity reduction Dominic DICLEMENTE 2020-12-01
10211972 Deserialized dual-loop clock radio and data recovery circuit Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang Wook Park 2019-02-19
9716582 Deserialized dual-loop clock radio and data recovery circuit Mehrdad Ramezani, David J. Cassan, Christopher D. Holdenried, Sang Wook Park 2017-07-25
8879618 Decision feedback equalizer and transceiver Mohamed Ahmed Youssef Abdalla, Afshin Rezayee, David J. Cassan, Chris Holdenried, Saman Sadr 2014-11-04