Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425014 | Self-aligning interconnect for a digital system | Marcus Van Ierssel, Vikram Karvat, Brian Che Yuen Lam, David M. Moore, Saif Elam | 2025-09-23 |
| 12366882 | Field programmable platform array | Mohammad Faisal | 2025-07-22 |
| 12019464 | Digital system synchronization | Mohammad Faisal, David M. Moore, Yu-Hui Huang | 2024-06-25 |
| 11979165 | Frequency multiplier circuit with programmable frequency transition controller | Scott Howe, Xiao Wu | 2024-05-07 |
| 11831318 | Frequency multiplier system with multi-transition controller | Scott Howe, Xiao Wu | 2023-11-28 |
| 11496139 | Frequency measurement circuit with adaptive accuracy | Xiao Wu | 2022-11-08 |
| 11493950 | Frequency counter circuit for detecting timing violations | Xiao Wu | 2022-11-08 |
| 11374578 | Zero-offset phase detector apparatus and method | Chun-Ju Chou, Yuxiang Mu | 2022-06-28 |
| 11165432 | Glitch-free digital controlled delay line apparatus and method | Chun-Ju Chou, Yuxiang Mu | 2021-11-02 |
| 11128308 | Regulated charge sharing apparatus and methods | Yuxiang Mu, Noman Hai | 2021-09-21 |
| 11070216 | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization | Frederick Christopher Candler | 2021-07-20 |
| 11070215 | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization | Frederick Christopher Candler | 2021-07-20 |
| 11017138 | Timing analysis for parallel multi-state driver circuits | Muhammad Faisal, David M. Moore, Ramin Shirani | 2021-05-25 |
| 10972119 | Regulated charge sharing analog-to-digital converter (ADC) apparatus and methods | Yuxiang Mu, Noman Hai | 2021-04-06 |
| 10972115 | Methods and apparatus for calibrating a regulated charge sharing analog-to-digital converter (ADC) | Yuxiang Mu, Noman Hai | 2021-04-06 |
| 10972106 | Phase and delay compensation circuit and method | Chun-Ju Chou, Yuxiang Mu | 2021-04-06 |
| 10740526 | Integrated circuit design system with automatic timing margin reduction | Muhammad Faisal, David M. Moore, Ramin Shirani, Yu-Hui Huang | 2020-08-11 |
| 10713409 | Integrated circuit design system with automatic timing margin reduction | Muhammad Faisal, David M. Moore, Ramin Shirani, Yu-Hui Huang | 2020-07-14 |
| 10614182 | Timing analysis for electronic design automation of parallel multi-state driver circuits | Muhammad Faisal, David M. Moore, Ramin Shirani | 2020-04-07 |
| 10594323 | Locked loop circuit and method with digitally-controlled oscillator (DCO) gain normalization | Frederick Christopher Candler | 2020-03-17 |
| 10587275 | Locked loop circuit with configurable second error input | Muhammad Faisal | 2020-03-10 |
| 10158365 | Digital, reconfigurable frequency and delay generator with phase measurement | Muhammad Faisal | 2018-12-18 |
| 10031992 | Concurrently optimized system-on-chip implementation with automatic synthesis and integration | Muhammad Faisal, David M. Moore, Ramin Shirani | 2018-07-24 |
| 9762249 | Reconfigurable phase-locked loop | Muhammad Faisal, David M. Moore | 2017-09-12 |
| 9705516 | Reconfigurable phase-locked loop with optional LC oscillator capability | Muhammad Faisal, David M. Moore | 2017-07-11 |