MF

Muhammad Faisal

MC Movellus Circuits: 10 patents #3 of 16Top 20%
MT Motive Technologies: 3 patents #5 of 15Top 35%
KAIST: 2 patents #4,169 of 11,619Top 40%
University of Michigan: 2 patents #1,079 of 4,352Top 25%
Overall (All Time): #268,162 of 4,157,543Top 7%
17
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12062243 Distracted driving detection using a multi-task training process Ali HASSAN, Ijaz AKHTER, Afsheen Rafaqat ALI, Ahmed Mohamed Abdelatty Ali 2024-08-13
11989927 Apparatus and method for detecting keypoint based on deep learning using information change across receptive fields Yong Ju Cho, Jeong-Il Seo, Rehan Hafiz, Mohsen Ali, Usama Sadiq +1 more 2024-05-21
11798298 Distracted driving detection using a multi-task training process Ali HASSAN, Ijaz AKHTER, Afsheen Rafaqat ALI, Ahmed Mohamed Abdelatty Ali 2023-10-24
11720790 Method of training image deep learning model and device thereof Yong Ju Cho, Jeong-Il Seo, Rehan Hafiz, Mohsen Ali, Aman Irshad 2023-08-08
11532169 Distracted driving detection using a multi-task training process Ali HASSAN, Ijaz AKHTER, Afsheen Rafaqat ALI, Ahmed Mohamed Abdelatty Ali 2022-12-20
11017138 Timing analysis for parallel multi-state driver circuits Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani 2021-05-25
10740526 Integrated circuit design system with automatic timing margin reduction Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani, Yu-Hui Huang 2020-08-11
10713409 Integrated circuit design system with automatic timing margin reduction Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani, Yu-Hui Huang 2020-07-14
10614182 Timing analysis for electronic design automation of parallel multi-state driver circuits Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani 2020-04-07
10587275 Locked loop circuit with configurable second error input Jeffrey Alan Fredenburg 2020-03-10
10158365 Digital, reconfigurable frequency and delay generator with phase measurement Jeffrey Alan Fredenburg 2018-12-18
10031992 Concurrently optimized system-on-chip implementation with automatic synthesis and integration Jeffrey Alan Fredenburg, David M. Moore, Ramin Shirani 2018-07-24
9762249 Reconfigurable phase-locked loop Jeffrey Alan Fredenburg, David M. Moore 2017-09-12
9705516 Reconfigurable phase-locked loop with optional LC oscillator capability Jeffrey Alan Fredenburg, David M. Moore 2017-07-11
9680480 Fractional and reconfigurable digital phase-locked loop Jeffrey Alan Fredenburg, David M. Moore 2017-06-13
9641183 Dual-loop programmable and dividerless clock generator for ultra low power applications David D. Wentzloff 2017-05-02
9515668 Automatically placed-and-routed ADPLL with PWM-based DCO resolution enhancement David D. Wentzloff 2016-12-06