PK

Prabhnoor Singh Kainth

CS Cadence Design Systems: 1 patents #1,216 of 2,263Top 55%
📍 Toronto, CA: #5,171 of 9,482 inventorsTop 55%
Overall (All Time): #2,623,641 of 4,157,543Top 65%
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Showing 1–1 of 1 patents

Patent #TitleCo-InventorsDate
11831323 Methods and circuits for reducing clock jitter Marcus Van Ierssel, Nanyan Wang 2023-11-28