Issued Patents All Time
Showing 126–138 of 138 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6952431 | Clock multiplying delay-locked loop for data communications | William J. Dally | 2005-10-04 |
| 6937073 | Frequency multiplier with phase comparator | William J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu | 2005-08-30 |
| 6861916 | Phase controlled oscillator circuit with input signal coupler | William J. Dally, Ramin Farjad-Rad, Thomas Hastings Greer, III, Hiok-Tiaq Ng, Teva J. Stone | 2005-03-01 |
| 6807186 | Architectures for a single-stage grooming switch | William J. Dally, John H. Edmondson, Donald A. Priore, Ephrem C. Wu | 2004-10-19 |
| 6674772 | Data communications circuit with multi-stage multiplexing | William J. Dally | 2004-01-06 |
| 6617936 | Phase controlled oscillator | William J. Dally, Ramin Farjad-Rad, Thomas Hastings Greer, III, Hiok-Tiaq Ng, Teva J. Stone | 2003-09-09 |
| 6556628 | Methods and systems for transmitting and receiving differential signals over a plurality of conductors | Stephen G. Tell, Robert E. Palmer | 2003-04-29 |
| 6476656 | Low-power low-jitter variable delay timing circuit | William J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu | 2002-11-05 |
| 6316987 | Low-power low-jitter variable delay timing circuit | William J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu | 2001-11-13 |
| 6275072 | Combined phase comparator and charge pump circuit | William J. Dally, Ramin Farjad-Rad, Teva J. Stone, Xiaoying Yu | 2001-08-14 |
| 5481669 | Architecture and apparatus for image generation utilizing enhanced memory devices | Steven E. Molnar, John Eyles | 1996-01-02 |
| 5388206 | Architecture and apparatus for image generation | Steven E. Molnar, John Eyles | 1995-02-07 |
| 4783649 | VLSI graphics display image buffer using logic enhanced pixel memory cells | Henry Fuchs | 1988-11-08 |