Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12191868 | Frequency-locked and phase-locked loop-based clock glitch detection for security | Sanquan Song, Nikola Nedovic | 2025-01-07 |
| 12033060 | Asynchronous accumulator using logarithmic-based arithmetic | William J. Dally, Rangharajan Venkatesan, Brucek Kurdo Khailany | 2024-07-09 |
| 11962312 | Frequency-locked and phase-locked loop-based clock glitch detection for security | Sanquan Song, Nikola Nedovic | 2024-04-16 |
| 11784835 | Detection and mitigation of unstable cells in unclonable cell array | Sudhir Shrikantha Kudva, Nikola Nedovic, Carl Thomas Gray | 2023-10-10 |
| 11681342 | Memory controller with processor for generating interface adjustment signals | — | 2023-06-20 |
| 11133794 | Signal calibration circuit | Matthew Rudolph Fojtik, John W. Poulton | 2021-09-28 |
| 10999051 | Reference noise compensation for single-ended signaling | Xi Chen, Nikola Nedovic, Carl Thomas Gray | 2021-05-04 |
| 10965440 | Reference noise compensation for single-ended signaling | Xi Chen, Nikola Nedovic, Carl Thomas Gray | 2021-03-30 |
| 10884465 | Memory controller with processor for generating interface adjustment signals | — | 2021-01-05 |
| 10644686 | Self-clocking sampler with reduced metastability | John W. Poulton, Sudhir Shrikantha Kudva, John M. Wilson | 2020-05-05 |
| 10601409 | Self-clocking sampler with reduced metastability | John W. Poulton, Sudhir Shrikantha Kudva, John M. Wilson | 2020-03-24 |
| 9965008 | Memory controller with processor for generating interface adjustment signals | — | 2018-05-08 |
| 9471091 | Periodic synchronizer using a reduced timing margin to generate a speculative synchronized output signal that is either validated or recalled | William J. Dally | 2016-10-18 |
| 9164134 | High-resolution phase detector | William J. Dally | 2015-10-20 |
| 9117031 | Generating interface adjustment signals in a device-to-device interconnection system | — | 2015-08-25 |
| 9100094 | System and method for tuning a serial link | John W. Poulton | 2015-08-04 |
| 8964919 | System and method for determining a time for safely sampling a signal of a clock domain | — | 2015-02-24 |
| 8879681 | System and method for determining a time for safely sampling a signal of a clock domain | William J. Dally | 2014-11-04 |
| 8782578 | Generating interface adjustment signals in a device-to-device interconnection system | — | 2014-07-15 |
| 8760204 | Variation-tolerant periodic synchronizer | William J. Dally | 2014-06-24 |
| 8428207 | System and method for determining a time for safely sampling a signal of a clock domain | William J. Dally | 2013-04-23 |
| 8365119 | Generating interface adjustment signals in a device-to-device interconnection system | — | 2013-01-29 |
| 7817767 | Processor-controlled clock-data recovery | Thomas Hastings Greer, III | 2010-10-19 |
| 7802212 | Processor controlled interface | Scott C. Best, John W. Poulton | 2010-09-21 |
| 7735037 | Generating interface adjustment signals in a device-to-device interconnection system | — | 2010-06-08 |