Issued Patents All Time
Showing 26–39 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8610307 | Optimized power supply for an electronic system | Jared L. Zerbe, Yohan Frans, Huy M. Nguyen | 2013-12-17 |
| 8553473 | Clock generator circuits with non-volatile memory for storing and/or feedback-controlling phase and frequency | Brent Haukness | 2013-10-08 |
| 8422590 | Apparatus and methods for differential signal receiving | Brian S. Leibowitz, Hae-Chang Lee | 2013-04-16 |
| 8362642 | Optimized power supply for an electronic system | Jared L. Zerbe, Yohan Frans, Huy M. Nguyen | 2013-01-29 |
| 8289032 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Hae-Chang Lee, Brian S. Leibowitz | 2012-10-16 |
| 8279976 | Signaling with superimposed differential-mode and common-mode signals | Qi Lin, Hae-Chang Lee, Brian S. Leibowitz, Jared L. Zerbe, Jihong Ren | 2012-10-02 |
| 8191022 | Stochastic steady state circuit analyses | Jihong Ren | 2012-05-29 |
| 8185853 | Transforming variable domains for linear circuit analysis | Kevin Dewayne Jones, Mark A. Horowitz | 2012-05-22 |
| 8159274 | Signaling with superimposed clock and data signals | Qi Lin, Brian S. Leibowitz, Jared L. Zerbe, Jihong Ren | 2012-04-17 |
| 8155174 | Hardware and method to test phase linearity of phase synthesizer | Hae-Chang Lee, Thomas Hastings Greer, III | 2012-04-10 |
| 8082528 | Process-independent schema library | — | 2011-12-20 |
| 7634039 | Delay-locked loop with dynamically biased charge pump | John George Maneatis, Daniel Karl Hartman | 2009-12-15 |
| 7627044 | Clock-edge modulated serial link with DC-balance control | Gyudong Kim, Won-Jun Choe, Deog-Kyoon Jeong, Bong-Joon Lee, Min-Kyu Kim | 2009-12-01 |
| 7602253 | Adaptive bandwidth phase locked loop with feedforward divider | Deog-Kyoon Jeong | 2009-10-13 |